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PIC16C433 Data Sheet
8-Bit CMOS Microcontroller with LIN Transceiver
2002 Microchip Technology Inc.
Preliminary
DS41139B
Note the following details of the code protection feature on Microchip devices: * * Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable."
*
* *
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products.
Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip's products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights.
Trademarks The Microchip name and logo, the Microchip logo, KEELOQ, MPLAB, PIC, PICmicro, PICSTART and PRO MATE are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, microID, MXDEV, MXLAB, PICMASTER, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. dsPIC, dsPICDEM.net, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, microPort, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, PICC, PICDEM, PICDEM.net, rfPIC, Select Mode and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. Serialized Quick Turn Programming (SQTP) is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2002, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999 and Mountain View, California in March 2002. The Company's quality system processes and procedures are QS-9000 compliant for its PICmicro(R) 8-bit MCUs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, non-volatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001 certified.
DS41139B - page ii
Preliminary
2002 Microchip Technology Inc.
PIC16C433
8-Bit CMOS Microcontroller with LIN Transceiver
Devices Included in this Data Sheet:
* PIC16C433
PIN DIAGRAM
PDIP, SOIC, Windowed CERDIP
LIN NC VSS VDD AVDD GP5/OSC1/CLKIN GP4/OSC2/AN3/CLKOUT GP3/MCLR/VPP NC
*1 2 3 4 5 6 7 8 9
High Performance RISC CPU:
* Only 35 single word instructions to learn * All instructions are single cycle (400 ns) except for program branches which are two-cycle * Operating speed: DC - 10 MHz clock input DC - 400 ns instruction cycle Device PIC16C433 * * * * * * Memory Program 2048 x 14 Data RAM 128 x 8
18 17 16 15 14 13 12 11 10
VBAT BACT VSS AVSS VSS GP0/AN0 GP1/AN1/VREF GP2/T0CKI/AN2/INT NC
PIC16C433
Note:
14-bit wide instructions 8-bit wide data path Interrupt capability Special function hardware registers 8-level deep hardware stack Direct, Indirect and Relative Addressing modes for data and instructions
Pins designated `NC' have no internal connection to the device.
Special Microcontroller Features:
* In-Circuit Serial ProgrammingTM (ICSPTM) * Internal 4 MHz oscillator with programmable calibration * Selectable clockout * Power-on Reset (POR) * Power-up Timer (PWRT) and Oscillator Start-up Timer (OST) * Watchdog Timer (WDT) with its own on-chip RC oscillator for reliable operation * Programmable code protection * Power saving SLEEP mode * Interrupt-on-pin change (GP0, GP1, GP3) * Internal pull-ups on I/O pins (GP0, GP1, GP3) * Internal pull-up on MCLR pin * Selectable oscillator options: - INTRC: Precision internal 4 MHz oscillator - EXTRC: External low cost RC oscillator - XT: Standard crystal/resonator - HS: High speed crystal/resonator - LP: Power saving, low frequency crystal
Peripheral Features:
* * * * * * * Integrated LIN bus transceiver Wake-up on bus activity 12V battery operation for transceiver Thermal Shutdown for transceiver Ground loss protection Four-channel, 8-bit A/D converter 8-bit real-time clock/counter (TMR0) with 8-bit programmable prescaler
CMOS Technology:
* Low power, high speed CMOS EPROM/ HV-CMOS technology * Fully static design * Operating voltage range 4.5V to 5.5V * Industrial and Extended temperature ranges * Low power consumption < 2 mA @ 5V, 4 MHz < 1 A typical standby current
2002 Microchip Technology Inc.
Preliminary
DS41139B-page 1
PIC16C433
Table of Contents 1.0 General Description.............................................................................................................................................. 3 2.0 PIC16C433 Device Varieties ................................................................................................................................ 5 3.0 Architectural Overview.......................................................................................................................................... 7 4.0 Memory Organization ......................................................................................................................................... 11 5.0 I/O Port ............................................................................................................................................................... 25 6.0 LIN Bus Transceiver ........................................................................................................................................... 33 7.0 Timer0 Module.................................................................................................................................................... 37 8.0 Analog-to-Digital Converter (A/D) Module .......................................................................................................... 43 9.0 Special Features of the CPU .............................................................................................................................. 51 10.0 Instruction Set Summary .................................................................................................................................... 67 11.0 Development Support......................................................................................................................................... 81 12.0 Electrical Specifications for PIC16C433 ............................................................................................................. 87 13.0 DC and AC Characteristics............................................................................................................................... 105 14.0 Packaging Information...................................................................................................................................... 111 Appendix A:Compatibility ............................................................................................................................................ 115 INDEX ......................................................................................................................................................................... 117 On-Line Support .......................................................................................................................................................... 121 Systems Information and Upgrade Hot Line ............................................................................................................... 121 Reader Response ....................................................................................................................................................... 122 Product Identification System...................................................................................................................................... 123
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DS41139B-page 2
Preliminary
2002 Microchip Technology Inc.
PIC16C433
1.0 GENERAL DESCRIPTION
The PIC16C433 device is a low cost, high performance, CMOS, fully static, 8-bit microcontroller with integrated analog-to-digital (A/D) converter and an integrated LIN bus Transceiver. The LIN physical layer is implemented in hardware with a voltage range from 0V to 18V, with a 40V transient capability. The LIN protocol is to be implemented in firmware, which enables flexibility with future revisions of the LIN protocol. All PICmicro(R) microcontrollers employ an advanced RISC architecture. The PIC16C433 microcontroller has enhanced core features, eight-level deep stack, and multiple internal and external interrupt sources. The separate instruction and data buses of the Harvard architecture allow a 14-bit wide instruction word with the separate 8-bit wide data. The two stage instruction pipeline allows all instructions to execute in a single cycle, except for program branches, which require two cycles. A total of 35 instructions (reduced instruction set) are available. Additionally, a large register set gives some of the architectural innovations used to achieve a very high performance. PIC16C433 microcontroller typically achieve a 2:1 code compression and a 4:1 speed improvement over other 8-bit microcontrollers in their class. The PIC16C433 device has 128 bytes of RAM, 5 I/O pins and 1 input pin. In addition, a timer/counter is available. Also a 4-channel, high speed, 8-bit A/D is provided. The 8-bit resolution is ideally suited for applications requiring low cost analog interface (i.e., thermostat control, pressure sensing, etc.) The PIC16C433 device has special features to reduce external components, thus reducing cost, enhancing system reliability and reducing power consumption. The Power-on Reset (POR), Power-up Timer (PWRT), and Oscillator Start-up Timer (OST) eliminate the need for external RESET circuitry. There are five oscillator configurations to choose from, including INTRC precision internal Oscillator mode and the power saving LP (Low Power) Oscillator mode. Power saving SLEEP mode, Watchdog Timer and code protection features improve system cost, power and reliability. The SLEEP (power-down) feature provides a Power Saving mode. The user can wake-up the chip from SLEEP through several external and internal interrupts and RESETS. A highly reliable Watchdog Timer with its own on-chip RC oscillator provides protection against software lockup. A UV erasable windowed package version is ideal for code development, while the cost-effective One-TimeProgrammable (OTP) version is suitable for production in any volume. The customer can take full advantage of Microchip's price leadership in OTP microcontrollers, while benefiting from the OTP's flexibility.
1.1
Applications
The PIC16C433 microcontroller fits well in applications ranging from automotive applications to home appliance applications. The EPROM technology makes customizing application programs extremely fast. The small footprint packages, for through hole or surface mounting, make this microcontroller series perfect for applications with space limitations. Low cost, low power, high performance, ease of use and I/O flexibility make the PIC16C433 series very versatile even in areas where no microcontroller use has been considered before (i.e., timer functions, replacement of glue logic and PLD's in larger systems, coprocessor applications).
1.2
Development Support
The PIC16C433 device is supported by a full featured macro assembler, a software simulator, an in-circuit emulator, a low cost development programmer and a full featured programmer. A "C" compiler and fuzzy logic support tools are also available.
2002 Microchip Technology Inc.
Preliminary
DS41139B-page 3
PIC16C433
NOTES:
DS41139B-page 4
Preliminary
2002 Microchip Technology Inc.
PIC16C433
2.0 PIC16C433 DEVICE VARIETIES
2.3
A variety of frequency ranges and packaging options are available. Depending on application and production requirements, the proper device option can be selected using the information in the PIC16C433 Product Identification System (page 123) at the end of this data sheet. When placing orders, please use that page of the data sheet to specify the correct part number.
Quick-Turn-Programming (QTP) Devices
2.1
UV Erasable Devices
The UV erasable version, offered in windowed package, is optimal for prototype development and pilot programs. The UV erasable version can be erased and reprogrammed to any of the configuration modes. Microchip's PRO MATE II device programmer supports the PIC16C433. Third party programmers also are available; refer to the Microchip Third Party Guide (DS00104) for a list of sources. Note: Please note that erasing the device will also erase the pre-programmed internal calibration value for the internal oscillator. The calibration value must be saved prior to erasing the part.
Microchip offers a QTP Programming Service for factory production orders. This service is made available for users who choose not to program a medium to high quantity of units and whose code patterns have stabilized. The devices are identical to the OTP devices, but with all EPROM locations and configuration options already programmed by the factory. Certain code and prototype verification procedures apply before production shipments are available. Please contact your local Microchip Technology sales office for more details.
2.4
Serialized Quick-Turn Programming (SQTPSM) Devices
Microchip offers a unique programming service where a few user defined locations in each device are programmed with different serial numbers. The serial numbers may be random, pseudo-random, or sequential. Serial programming allows each device to have a unique number which can serve as an entry code, password, or ID number.
2.2
One-Time-Programmable (OTP) Devices
The availability of OTP devices is especially useful for customers who need the flexibility for frequent code updates and small volume applications. The OTP devices, packaged in plastic packages, permit the user to program them once. In addition to the program memory, the configuration bits must also be programmed.
2002 Microchip Technology Inc.
Preliminary
DS41139B-page 5
PIC16C433
NOTES:
DS41139B-page 6
Preliminary
2002 Microchip Technology Inc.
PIC16C433
3.0 ARCHITECTURAL OVERVIEW
The high performance of the PIC16C433 family can be attributed to a number of architectural features commonly found in RISC microprocessors. To begin with, the PIC16C433 uses a Harvard architecture in which program and data are accessed from separate memories using separate buses. This improves bandwidth over traditional von Neumann architecture in which program and data are fetched from the same memory using the same bus. Separating program and data buses also allow instructions to be sized differently than the 8-bit wide data word. Instruction opcodes are 14-bits wide making it possible to have all single word instructions. A 14-bit wide program memory access bus fetches a 14-bit instruction in a single instruction cycle. A two-stage pipeline overlaps fetch and execution of instructions (Example 3-1). Consequently, all instructions (35) execute in a single cycle (400 ns @ 10 MHz) except for program branches. The PIC16C433 can directly or indirectly address its register files or data memory. All special function registers, including the program counter, are mapped in the data memory. The PIC16C433 has an orthogonal (symmetrical) instruction set that makes it possible to carry out any operation on any register using any Addressing mode. This symmetrical nature and lack of `special optimal situations' make programming with the PIC16C433 simple, yet efficient. In addition, the learning curve is reduced significantly. PIC16C433 devices contain an 8-bit ALU and working register. The ALU is a general purpose arithmetic unit. It performs arithmetic and Boolean functions between the data in the working register and any register file. The ALU is 8 bits wide and capable of addition, subtraction, shift and logical operations. Unless otherwise mentioned, arithmetic operations are two's complement in nature. In two-operand instructions, typically one operand is the working register (W register). The other operand is a file register, or an immediate constant. In single operand instructions, the operand is either the W register or a file register. The W register is an 8-bit working register used for ALU operations. It is not an addressable register. Depending on the instruction executed, the ALU may affect the values of the Carry (C), Digit Carry (DC), and Zero (Z) bits in the STATUS register. The C and DC bits operate as a borrow bit and a digit borrow out bit, respectively, in subtraction. See the SUBLW and SUBWF instructions for examples.
2002 Microchip Technology Inc.
Preliminary
DS41139B-page 7
PIC16C433
FIGURE 3-1: PIC16C433 BLOCK DIAGRAM
Device PIC16C433
Program Memory 2K x 14
Data Memory (RAM) 128 x 8
13 Program Counter EPROM Program Memory 2K x 14
Data Bus
8
GPIO GP0/AN0 GP1/AN1/VREF GP2/T0CKI/AN2/INT GP3/MCLR/VPP GP4/OSC2/AN3/CLKOUT GP5/OSC1/CLKIN LINTX LINRX
8-Level Stack (13-bit)
RAM 128 bytes File Registers RAM Addr(1) 9
Program Bus
14 Instruction reg Direct Addr 7
Addr MUX 8 Indirect Addr
FSR reg STATUS reg
LIN bus Transceiver
LIN bus VBAT BACT
8 3
Power-up Timer Instruction Decode & Control OSC1/CLKIN OSC2/CLKOUT Internal 4 MHz Clock Timing Generation Oscillator Start-up Timer Watchdog Timer Power-on Reset 8
MUX
ALU
W reg
MCLR VDD, VSS
Timer0
A/D
Note 1: Higher order bits are from the STATUS Register.
DS41139B-page 8
Preliminary
2002 Microchip Technology Inc.
PIC16C433
TABLE 3-1:
Name GP0/AN0
PIC16C433 PINOUT DESCRIPTION
DIP Pin # 13 I/O/P Type I/O Buffer Type Description
TTL/ST Bi-directional I/O port/serial programming data/analog input 0. Can be software programmed for internal weak pull-up and interrupt-on-pin change. This buffer is a Schmitt Trigger input when used in Serial Programming mode. TTL/ST Bi-directional I/O port/serial programming clock/analog input 1/voltage reference. Can be software programmed for internal weak pull-up and interrupt-on-pin change. This buffer is a Schmitt Trigger input when used in Serial Programming mode. ST Bi-directional I/O port/analog input 2. Can be configured as T0CKI or external interrupt.
GP1/AN1/VREF
12
I/O
GP2/T0CKI/AN2/INT GP3/MCLR/VPP
11 8
I/O I
TTL/ST Input port/Master Clear (Reset) input/programming voltage input. When configured as MCLR, this pin is an active low RESET to the device. Voltage on MCLR/VPP must not exceed VDD during normal device operation. Can be software programmed for internal weak pull-up and interrupton-pin change. Weak pull-up always on if configured as MCLR. This buffer is Schmitt Trigger when in MCLR mode. TTL Bi-directional I/O port/oscillator crystal output/analog input 3. Connections to crystal or resonator in Crystal Oscillator mode (HS, XT and LP modes only, GPIO in other modes). In EXTRC and INTRC modes, the pin output can be configured to CLKOUT, which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate.
GP4/OSC2/AN3/CLKOUT
7
I/O
GP5/OSC1/CLKIN
6
I/O
TTL/ST Bi-directional IO port/oscillator crystal input/external clock source input (GPIO in INTRC mode only, OSC1 in all other oscillator modes). Schmitt Trigger input for EXTRC Oscillator mode. HV/OD High voltage bi-directional bus interface. -- TTL -- -- -- -- Battery input voltage. Bus activity output pin. It is a CMOS-levels representation of the LIN pin. Positive supply for logic and I/O pins. Ground reference for logic and I/O pins. Analog positive supply. Analog ground.
LIN VBAT BACT VDD VSS AVDD AVSS
1 18 17 4 3,14,16 5 15
I/O P O P P P P
Legend: I = Input, O = Output, I/O = Input/Output, P = Power, -- = not used, TTL = TTL input, ST = Schmitt Trigger input, OD = Open Drain
2002 Microchip Technology Inc.
Preliminary
DS41139B-page 9
PIC16C433
3.1 Clocking Scheme/Instruction Cycle 3.2 Instruction Flow/Pipelining
The clock input (from OSC1) is internally divided by four to generate four non-overlapping quadrature clocks, namely Q1, Q2, Q3 and Q4. Internally, the program counter (PC) is incremented every Q1, and the instruction is fetched from the program memory and latched into the instruction register in Q4. The instruction is decoded and executed during the following Q1 through Q4. The clocks and instruction execution flow is shown in Figure 3-2. An Instruction Cycle consists of four Q cycles (Q1, Q2, Q3 and Q4). The instruction fetch and execute are pipelined such that fetch takes one instruction cycle, while decode and execute takes another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the program counter to change (i.e., GOTO), then two cycles are required to complete the instruction (Example 3-1). A fetch cycle begins with the program counter (PC) incrementing in Q1. In the execution cycle, the fetched instruction is latched into the Instruction Register (IR) in cycle Q1. This instruction is then decoded and executed during the Q2, Q3, and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write).
FIGURE 3-2:
CLOCK/INSTRUCTION CYCLE
Q1 OSC1 Q1 Q2 Q3 Q4 PC PC PC+1 PC+2 Internal Phase Clock Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC2/CLKOUT (EXTRC and INTRC modes)
Fetch INST (PC) Execute INST (PC-1)
Fetch INST (PC+1) Execute INST (PC)
Fetch INST (PC+2) Execute INST (PC+1)
EXAMPLE 3-1:
INSTRUCTION PIPELINE FLOW
TCY0 TCY1 Execute 1 Fetch 2 Execute 2 Fetch 3 Execute 3 Fetch 4 Flush Fetch SUB_1 Execute SUB_1 TCY2 TCY3 TCY4 TCY5
1. MOVLW 55h 2. MOVWF GPIO 3. CALL 4. BSF SUB_1
Fetch 1
GPIO, BIT3 (Forced NOP)
5. Instruction @ address SUB_1
All instructions are single cycle, except for any program branches. These take two cycles since the fetched instruction is "flushed" from the pipeline while the new instruction is being fetched and then executed.
DS41139B-page 10
Preliminary
2002 Microchip Technology Inc.
PIC16C433
4.0
4.1
MEMORY ORGANIZATION
Program Memory Organization
4.2
Data Memory Organization
The PIC16C433 has a 13-bit program counter capable of addressing an 8K x 14 program memory space. For the PIC16C433, the first 2K x 14 (0000h-07FFh) is implemented. Accessing a location above the physically implemented address will cause a wraparound. The RESET Vector is at 0000h and the interrupt vector is at 0004h.
The data memory is partitioned into two banks, which contain the General Purpose Registers and the Special Function Registers. Bit RP0 is the bank select bit. RP0 (STATUS<5>) = 1 Bank 1 RP0 (STATUS<5>) = 0 Bank 0 Each Bank extends up to 7Fh (128 bytes). The lower locations of each Bank are reserved for the Special Function Registers. Above the Special Function Registers are General Purpose Registers implemented as static RAM. Both Bank 0 and Bank 1 contain Special Function Registers. Some "high use" Special Function Registers from Bank 0 are mirrored in Bank 1 for code reduction and quicker access. Also note that F0h through FFh on the PIC16C433 is mapped into Bank 0 registers 70h-7Fh as common RAM. 4.2.1 GENERAL PURPOSE REGISTER FILE
FIGURE 4-1:
PIC16C433 PROGRAM MEMORY MAP AND STACK
PC<12:0>
CALL, RETURN RETFIE, RETLW
13
Stack Level 1
Stack Level 8 RESET Vector
The register file can be accessed either directly or indirectly through the File Select Register FSR (Section 4.5). 0000h
Peripheral Interrupt Vector
0004h 0005h
On-Chip Program Memory
03FFh 0400h 07FFh 0800h
1FFFh
2002 Microchip Technology Inc.
Preliminary
DS41139B-page 11
PIC16C433
FIGURE 4-2:
File Address 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h INDF(1) TMR0 PCL STATUS FSR GPIO INDF(1) OPTION PCL STATUS FSR TRIS
PIC16C433 REGISTER FILE MAP
File Address 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh A0h
4.2.2
SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by the CPU and Peripheral Modules for controlling the desired operation of the device. These registers are implemented as static RAM. The Special Function Registers can be classified into two sets (core and peripheral). Those registers associated with the "core" functions are described in this section, and those related to the operation of the peripheral features are described in the section of that peripheral feature.
PCLATH INTCON PIR1
PCLATH INTCON PIE1 PCON OSCCAL
ADRES ADCON0
ADCON1 General Purpose Register
General Purpose Register 70h 7Fh Bank 0 Mapped in Bank 0 Bank 1
BFh C0h EFh F0h FFh
Unimplemented data memory locations, read as '0'. Note 1: Not a physical register.
DS41139B-page 12
Preliminary
2002 Microchip Technology Inc.
PIC16C433
TABLE 4-1:
Address Name
PIC16C433 SPECIAL FUNCTION REGISTER SUMMARY
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Power-on Reset Value on all other RESETS(3)
Bank 0 00h(1) 01h 02h
(1)
INDF TMR0 PCL STATUS FSR GPIO -- -- -- --
Addressing this location uses contents of FSR to address data memory (not a physical register) Timer0 module's register Program Counter's (PC) Least Significant Byte IRP(4) RP1(4) RP0 TO PD Z DC C
0000 0000 xxxx xxxx 0000 0000 0001 1xxx xxxx xxxx
0000 0000 uuuu uuuu 0000 0000 000q quuu uuuu uuuu 11uu uuuu -- -- -- -- ---0 0000 0000 000u -0-- ----- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- uuuu uuuu 0000 0000
03h(1) 04h(1) 05h 06h 07h 08h 09h 0Ah
(1,2)
Indirect data memory address pointer LINTX LINRX GP5 GP4 GP3 GP2 GP1 GP0
11xx xxxx -- -- -- --
Unimplemented Unimplemented Unimplemented Unimplemented -- GIE -- -- PEIE ADIF -- T0IE -- Write Buffer for the upper 5 bits of the Program Counter INTE -- GPIE -- T0IF -- INTF -- GPIF --
PCLATH INTCON PIR1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- ADRES ADCON0
---0 0000 0000 000x -0-- ----- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- xxxx xxxx
0Bh(1) 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh Legend: Note 1: 2: 3: 4:
Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented A/D Result Register ADCS1 ADCS0 reserved CHS1 CHS0 GO/DONE reserved ADON
0000 0000
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'. Shaded locations are unimplemented, read as `0'. These registers can be addressed from either bank. The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose contents are transferred to the upper byte of the program counter. Other (non Power-up) Resets include external RESET through MCLR and Watchdog Timer Reset. The IRP and RP1 bits are reserved on the PIC16C433; always maintain these bits clear.
2002 Microchip Technology Inc.
Preliminary
DS41139B-page 13
PIC16C433
TABLE 4-1:
Address Name
PIC16C433 SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Power-on Reset Value on all other RESETS(3)
Bank 1 80h(1) 81h 82h(1) 83h
(1)
INDF OPTION PCL STATUS FSR TRIS -- -- -- -- PCLATH INTCON PIE1 -- PCON OSCCAL -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- ADCON1
Addressing this location uses contents of FSR to address data memory (not a physical register) GPPU INTEDG T0CS T0SE PSA PS2 PS1 PS0
0000 0000 1111 1111 0000 0000
0000 0000 1111 1111 0000 0000 000q quuu uuuu uuuu --11 1111 -- -- -- -- ---0 0000 0000 000u -0-- ----- ---- --uuuuu uu--- -- -- -- -- -- -- -- -- -- -- -- -- -- -- ---- -000
Program Counter's (PC) Least Significant Byte IRP
(4)
RP1
(4)
RP0
TO
PD
Z
DC
C
0001 1xxx xxxx xxxx --11 1111 -- -- -- --
84h(1) 85h 86h 87h 88h 89h 8Ah(1,2) 8Bh(1) 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh Legend: Note 1: 2: 3: 4:
Indirect data memory address pointer -- Unimplemented Unimplemented Unimplemented Unimplemented -- GIE -- -- PEIE ADIE -- T0IE -- Write Buffer for the upper 5 bits of the PC INTE -- GPIE -- T0IF -- INTF -- GPIF -- -- GPIO Data Direction Register
---0 0000 0000 000x -0-- -----
Unimplemented -- CAL3 -- CAL2 -- CAL1 -- CAL0 -- CALFST -- CALSLW POR -- -- --
---- --00111 00--- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented -- -- -- -- -- PCFG2 PCFG1 PCFG0
---- -000
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'. Shaded locations are unimplemented, read as `0'. These registers can be addressed from either bank. The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose contents are transferred to the upper byte of the program counter. Other (non Power-up) Resets include external RESET through MCLR and Watchdog Timer Reset. The IRP and RP1 bits are reserved on the PIC16C433; always maintain these bits clear.
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PIC16C433
4.2.2.1 STATUS Register The STATUS Register, shown in Register 4-1, contains the arithmetic status of the ALU, the RESET status and the bank select bits for data memory. The STATUS Register can be the destination for any instruction, as with any other register. If the STATUS Register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable. Therefore, the result of an instruction with the STATUS Register as destination may be different than intended. For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS Register as 000u u1uu (where u = unchanged). It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the STATUS Register, because these instructions do not affect the Z, C or DC bits from the STATUS Register. For other instructions, not affecting any status bits, see the "Instruction Set Summary." Note 1: Bits IRP and RP1 (STATUS<7:6>) are not used by the PIC16C433 and should be maintained clear. Use of these bits as general purpose R/W bits is NOT recommended, since this may affect upward compatibility with future products. 2: The C and DC bits operate as a borrow and digit borrow bit, respectively, in subtraction. See the SUBLW and SUBWF instructions for examples.
REGISTER 4-1: STATUS REGISTER (ADDRESS 03h, 83h)
Reserved IRP bit7 bit 7 IRP: Register Bank Select bit (used for indirect addressing) 1 = Bank 2, 3 (100h - 1FFh) 0 = Bank 0, 1 (00h - FFh) The IRP bit is reserved, always maintain this bit clear RP1:RP0: Register Bank Select bits (used for direct addressing) 11 = Bank 3 (180h - 1FFh) 10 = Bank 2 (100h - 17Fh) 01 = Bank 1 (80h - FFh) 00 = Bank 0 (00h - 7Fh) Each bank is 128 bytes. The RP1 bit is reserved, always maintain this bit clear. TO: Timeout bit 1 = After power-up, CLRWDT instruction, or SLEEP instruction 0 = A WDT timeout occurred PD: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero DC: Digit Carry/borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions) (for borrow the polarity is reversed) 1 = A carry-out from the 4th low order bit of the result occurred 0 = No carry-out from the 4th low order bit of the result C: Carry/borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions) 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred Note: For borrow, the polarity is reversed. A subtraction is executed by adding the two's complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of the source register. Reserved RP1 R/W-0 RP0 R-1 TO R-1 PD R/W-x Z R/W-x DC R/W-x C bit0
bit 6-5
bit 4
bit 3
bit 2
bit 1
bit 0
Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown
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PIC16C433
4.2.2.2 OPTION Register Note: To achieve a 1:1 prescaler assignment for the TMR0 register, assign the prescaler to the Watchdog Timer by setting bit PSA (OPTION<3>). The OPTION Register is a readable and writable register, which contains various control bits to configure the TMR0/WDT prescaler, the External INT Interrupt, TMR0 and the weak pull-ups on GPIO.
REGISTER 4-2: OPTION REGISTER (ADDRESS 81h))
R/W-1 GPPU bit7 bit 7 GPPU: Weak Pull-up Enable bit 1 = Weak pull-ups disabled 0 = Weak pull-ups enabled (GP0, GP1, GP3) INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of GP2/T0CKI/AN2/INT pin 0 = Interrupt on falling edge of GP2/T0CKI/AN2/INT pin T0CS: TMR0 Clock Source Select bit 1 = Transition on GP2/T0CKI/AN2/INT pin 0 = Internal instruction cycle clock (CLKOUT) T0SE: TMR0 Source Edge Select bit 1 = Increment on high-to-low transition on GP2/T0CKI/AN2/INT pin 0 = Increment on low-to-high transition on GP2/T0CKI/AN2/INT pin PSA: Prescaler Assignment bit 1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module PS<2:0>: Prescaler Rate Select bits
Bit Value 000 001 010 011 100 101 110 111 TMR0 Rate 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 WDT Rate 1:1 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128
R/W-1 INTEDG
R/W-1 T0CS
R/W-1 T0SE
R/W-1 PSA
R/W-1 PS2
R/W-1 PS1
R/W-1 PS0 bit0
bit 6
bit 5
bit 4
bit 3
bit 2-0
Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown
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PIC16C433
4.2.2.3 INTCON Register Note: Interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). The INTCON Register is a readable and writable register, which contains various enable and flag bits for the TMR0 Register overflow, GPIO port change and external GP2/INT pin interrupts.
REGISTER 4-3: INTCON REGISTER (ADDRESS 0Bh, 8Bh)
R/W-0 GIE bit7 bit 7 GIE: Global Interrupt Enable bit 1 = Enables all unmasked interrupts 0 = Disables all interrupts PEIE: Peripheral Interrupt Enable bit 1 = Enables all unmasked peripheral interrupts 0 = Disables all peripheral interrupts T0IE: TMR0 Overflow Interrupt Enable bit 1 = Enables the TMR0 interrupt 0 = Disables the TMR0 interrupt INTE: INT External Interrupt Enable bit 1 = Enables the external interrupt on GP2/INT/T0CKI/AN2 pin 0 = Disables the external interrupt on GP2/INT/T0CKI/AN2 pin GPIE: GPIO Interrupt-on-Change Enable bit 1 = Enables the GPIO Interrupt-on-Change 0 = Disables the GPIO Interrupt-on-Change T0IF: TMR0 Overflow Interrupt Flag bit 1 = TMR0 register has overflowed (must be cleared in software) 0 = TMR0 register did not overflow INTF: RB0/INT External Interrupt Flag bit 1 = The external interrupt on GP2/INT/T0CKI/AN2 pin occurred (must be cleared in software) 0 = The external interrupt on GP2/INT/T0CKI/AN2 pin did not occur GPIF: GPIO Interrupt-on-Change Flag bit 1 = GP0, GP1 or GP3 pins changed state (must be cleared in software) 0 = Neither GP0, GP1 nor GP3 pins have changed state Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown R/W-0 PEIE R/W-0 T0IE R/W-0 INTE R/W-0 GPIE R/W-0 T0IF R/W-0 INTF R/W-x GPIF bit0
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
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Preliminary
DS41139B-page 17
PIC16C433
4.2.2.4 PIE1 Register Note: This register contains the individual enable bits for the Peripheral interrupts. Bit PEIE (INTCON<6>) must be set to enable any peripheral interrupt.
REGISTER 4-4: PIE1 REGISTER (ADDRESS 8Ch))
U-0 -- bit7 bit 7 bit 6 Unimplemented: Read as '0' ADIE: A/D Converter Interrupt Enable bit 1 = Enables the A/D interrupt 0 = Disables the A/D interrupt Unimplemented: Read as '0' Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown R/W-0 ADIE U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit0
bit 5-0
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PIC16C433
4.2.2.5 PIR1 Register Note: This register contains the individual flag bits for the Peripheral interrupts. Interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
REGISTER 4-5: PIR1 REGISTER (ADDRESS 0Ch))
U-0 -- bit7 bit 7 bit 6 Unimplemented: Read as '0' ADIF: A/D Converter Interrupt Flag bit 1 = An A/D conversion completed (must be cleared in software) 0 = The A/D conversion is not complete Unimplemented: Read as '0' Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown R/W-0 ADIF U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit0
bit 5-0
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Preliminary
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PIC16C433
4.2.2.6 PCON Register The Power Control (PCON) Register contains a flag bit to allow differentiation between a Power-on Reset (POR), an external MCLR Reset and a WDT Reset.
REGISTER 4-6: PCON REGISTER (ADDRESS 8Eh))
U-0 -- bit7 bit 7-2 bit 1 Unimplemented: Read as '0' POR: Power-on Reset Status bit 1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) Unimplemented: Read as '0' Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 POR U-0 -- bit0
bit 0
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PIC16C433
4.2.2.7 OSCCAL Register The Oscillator Calibration (OSCCAL) Register is used to calibrate the internal 4 MHz oscillator. It contains four bits for fine calibration and two other bits to either increase or decrease frequency.
REGISTER 4-7: OSCCAL REGISTER (ADDRESS 8Fh)
R/W-0 CAL3 bit7 bit 7-4 bit 3 CAL<3:0>: Fine Calibration bits CALFST: Calibration Fast bit 1 = Increase frequency 0 = No change CALSLW: Calibration Slow bit 1 = Decrease frequency 0 = No change Unimplemented: Read as '0' Note: Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown If CALFST = 1 and CALSLW = 1, CALFST has precedence. R/W-1 CAL2 R/W-1 CAL1 R/W-1 CAL0 R/W-0 CALFST R/W-0 CALSLW U-0 -- U-0 -- bit0
bit 2
bit 1-0
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PIC16C433
4.3 PCL and PCLATH
4.3.2 STACK The Program Counter (PC) is 13-bits wide. The low byte comes from the PCL Register, which is a readable and writable register. The high byte (PC<12:8>) is not directly readable or writable and comes from PCLATH. On any RESET, the PC is cleared. Figure 4-3 shows the two situations for the loading of the PC. The upper example in Figure 4-3 shows how the PC is loaded on a write to PCL (PCLATH<4:0> PCH). The lower example in Figure 4-3 shows how the PC is loaded during a CALL or GOTO instruction (PCLATH<4:3> PCH). The PIC16C433 family has an 8-level deep x 13-bit wide hardware stack. The stack space is not part of either program or data space and the stack pointer is not readable or writable. The PC is PUSHed onto the stack when a CALL instruction is executed, or an interrupt causes a branch. The stack is POPed in the event of a RETURN, RETLW or a RETFIE instruction execution. PCLATH is not affected by a PUSH or POP operation. The stack operates as a circular buffer. This means that after the stack has been PUSHed eight times, the ninth push overwrites the value that was stored from the first push. The tenth push overwrites the second push (and so on). Note 1: There are no status bits to indicate stack overflow or stack underflow conditions.
Instruction with PCL as Destination ALU Result
FIGURE 4-3:
LOADING OF PC IN DIFFERENT SITUATIONS
PCL 8 7 0
PCH 12 PC 5
PCLATH<4:0>
8
PCLATH PCH 12 PC 2 PCLATH<4:3> 11 Opcode <10:0> PCLATH 11 10 8 7 PCL 0 GOTO, CALL
2: There are no instructions/mnemonics called PUSH or POP. These are actions that occur from the execution of the CALL, RETURN, RETLW, and RETFIE instructions, or the vectoring to an interrupt address.
4.4
Program Memory Paging
The PIC16C433 ignores both paging bits PCLATH<4:3>, which are used to access program memory when more than one page is available. The use of PCLATH<4:3> as general purpose read/write bits for the PIC16C433 is not recommended, since this may affect upward compatibility with future products.
4.3.1
COMPUTED GOTO
A Computed GOTO is accomplished by adding an offset to the program counter (ADDWF PCL). When doing a table read using a computed GOTO method, care should be exercised if the table location crosses a PCL memory boundary (each 256 byte block). Refer to the application note "Implementing a Table Read" (AN556).
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PIC16C433
4.5 Indirect Addressing, INDF and FSR Registers
A simple program to clear RAM locations 20h-2Fh using indirect addressing is shown in Example 4-1. The INDF Register is not a physical register. Addressing the INDF Register will cause indirect addressing. Any instruction using the INDF register actually accesses the register pointed to by the File Select Register, FSR. Reading the INDF register itself, indirectly (FSR = '0') will read 00h. Writing to the INDF register, indirectly results in a no-operation (although status bits may be affected). An effective 9-bit address is obtained by concatenating the 8-bit FSR register and the IRP bit (STATUS<7>), as shown in Figure 4-4. However, IRP is not used in the PIC16C433.
EXAMPLE 4-1:
movlw movwf NEXT clrf incf btfss goto CONTINUE :
INDIRECT ADDRESSING
0x20 FSR INDF FSR,F FSR,4 NEXT ;initialize pointer ;to RAM ;clear INDF register ;inc pointer ;all done? ;no clear next ;yes continue
FIGURE 4-4:
DIRECT/INDIRECT ADDRESSING
Direct Addressing Indirect Addressing
0 IRP(1) 7 FSR register 0
RP1 RP0(1)
6
from opcode
bank select
location select 00 00h 01 10 11
bank select 180h
location select
not used Data Memory
7Fh
1FFh
Bank 0 For register file map detail see Figure 4-2.
Bank 1
Bank 2
Bank 3
Note 1: The RP1 and IRP bits are reserved; always maintain these bits clear.
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Preliminary
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PIC16C433
NOTES:
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PIC16C433
5.0 I/O PORT
As with any other register, the I/O register can be written and read under program control. However, read instructions (i.e., MOVF GPIO,W) always read the I/O pins independent of the pin's Input/Output modes. On RESET, all I/O ports are defined as input (inputs are at hi-impedance), since the I/O control registers are all set. outputs are latched and remain unchanged until the output latch is rewritten. To use a port pin as output, the corresponding direction control bit in TRIS must be cleared (= 0). For use as an input, the corresponding TRIS bit must be set. Any I/O pin (except GP3) can be programmed individually as input or output. Port pins LINTX and LINRX are used for the LIN bus transceiver. These port pins are not available externally on the package. Users should avoid writing to pins GP6 (SDA) and GP7 (SCL), when not communicating with the LIN bus transceiver. Note: On a Power-on Reset, GP0, GP1, GP2 and GP4 are configured as analog inputs and read as '0'.
5.1
GPIO
GPIO is an 8-bit I/O register. Only the low order 6 bits are used (GP<5:0>). Bits 6 and 7 (LINTX and LINRX, respectively) are used by the LIN bus transceiver peripheral. Please note that GP3 is an input only pin. The configuration word can set several I/O's to alternate functions. When acting as alternate functions, the pins will read as `0' during port read. Pins GP0, GP1 and GP3 can be configured with weak pull-ups and also with interrupt-on-change. The interrupt-on-change and weak pull-up functions are not pin selectable. If pin 4 (GP3), is configured as MCLR, a weak pull-up is always on. Interrupt-on-change for this pin is not set and GP3 will read as '0'. Interrupt-on-change is enabled by setting bit GPIE, INTCON<3>. Note that external oscillator use overrides the GPIO functions on GP4 and GP5.
5.2
TRIS Register
This register controls the data direction for GPIO. A '1' from a TRIS Register bit puts the corresponding output driver in a Hi-impedance mode. A '0' puts the contents of the output data latch on the selected pins, enabling the output buffer. The exceptions are GP3, which is input only and its TRIS bit will always read as '1', while GP6 and GP7 TRIS bits will read as '0'. Note: A read of the ports reads the pins, not the output data latches. That is, if an output driver on a pin is enabled and driven high, but the external system is holding it low, a read of the port will indicate that the pin is low.
Upon RESET, the TRIS Register is all '1's, making all pins inputs. TRIS for pins GP4 and GP5 is forced to a '1', where appropriate. Writes to TRIS <5:4> will have an effect in EXTRC and INTRC oscillator modes only. When GP4 is configured as CLKOUT, changes to TRIS<4> will have no effect.
5.3
I/O Interfacing
The equivalent circuit for an I/O port pin is shown in Figure 5-1 through Figure 5-5. All port pins, except GP3, which is input only, may be used for both input and output operations. For input operations, these ports are non-latching. Any input must be present until read by an input instruction (i.e., MOVF GPIO,W). The
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Preliminary
DS41139B-page 25
PIC16C433
FIGURE 5-1: BLOCK DIAGRAM OF GP0/AN0 AND GP1/AN1/VREF PIN
GPPU
Data Bus D WR PORT CK Q Q VDD P VDD P VDD I/O Pin
Data Latch N
D WR TRIS CK
Q Q
VSS
VSS
TRIS Latch Analog Input Mode RD TRIS TTL Input Buffer
Q
D EN
RD PORT GP0/INT(1) and GP1/INT(1)
To A/D Converter
Note 1: Wake-up on pin change interrupts for GP0 and GP1.
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PIC16C433
FIGURE 5-2: BLOCK DIAGRAM OF GP2/T0CKI/AN2/INT PIN
Data Bus D WR PORT CK Q Q VDD P VDD I/O Pin
Data Latch N
D WR TRIS CK
Q Q
VSS
VSS
TRIS Latch Analog Input Mode RD TRIS Schmitt Trigger Input Buffer
Q
D EN
RD PORT TMR0 Clock Input GP2/INT To A/D Converter
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Preliminary
DS41139B-page 27
PIC16C433
FIGURE 5-3: BLOCK DIAGRAM OF GP3/MCLR/VPP PIN
VDD
GPPU MCLREN P Input Pin
VSS MCLR Schmitt Trigger Input Buffer Program Mode
HV Detect TTL Input Buffer
Data Bus Q D EN RD PORT
RD TRIS
VSS
GP3/INT(1)
Note 1: Wake-up on pin change interrupt for GP3.
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PIC16C433
FIGURE 5-4: BLOCK DIAGRAM OF GP4/OSC2/AN3/CLKOUT PIN
INTRC or EXTRC w/ CLKOUT CLKOUT (FOSC/4) 1
0
Data Bus WR PORT
From OSC1 D CK Q Q VDD P
Oscillator Circuit VDD I/O Pin
Data Latch N VSS D WR TRIS CK Q Q INTRC/ EXTRC VSS INTRC or EXTRC w/o CLKOUT Analog Input Mode
TRIS Latch
TTL Input Buffer
RD TRIS Q D EN RD PORT
To A/D Converter
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Preliminary
DS41139B-page 29
PIC16C433
FIGURE 5-5: BLOCK DIAGRAM OF GP5/OSC1/CLKIN PIN
To OSC2 Data Bus D WR PORT EN Q Q VDD P
Oscillator Circuit VDD
Data Latch I/O Pin
N D WR TRIS EN Q Q INTRC VSS VSS
TRIS Latch INTRC TTL Input Buffer RD TRIS
Q
D EN
RD PORT
TABLE 5-1:
SUMMARY OF PORT REGISTERS
Value on Power-on Reset --11 1111 PS1 DC GP1 PS0 C GP0 1111 1111 0001 1xxx 11xx xxxx Value on all other RESETS --11 1111 1111 1111 000q quuu 11uu uuuu
Address 85h 81h 03h 05h
Name TRIS OPTION STATUS GPIO
Bit 7 -- GPPU IRP
(1)
Bit 6 -- INTEDG RP1
(1)
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
GPIO Data Direction Register T0CS RP0 GP5 T0SE TO GP4 PSA PD GP3 PS2 Z GP2
LINTX
LINRX
Legend: Shaded cells not used by Port Registers, read as `0', -- = unimplemented, read as '0', x = unknown, u = unchanged, q = see tables in Section 9.4 for possible values. Note 1: The IRP and RP1 bits are reserved on the PIC16C433; always maintain these bits clear.
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PIC16C433
5.4
5.4.1
I/O Programming Considerations
BI-DIRECTIONAL I/O PORTS
Example 5-1 shows the effect of two sequential readmodify-write instructions on an I/O port.
Any instruction which writes, operates internally as a read followed by a write operation. The BCF and BSF instructions, for example, read the register into the CPU, execute the bit operation and write the result back to the register. Caution must be used when these instructions are applied to a port with both inputs and outputs defined. For example, a BSF operation on bit5 of GPIO will cause all eight bits of GPIO to be read into the CPU. Then, the BSF operation takes place on bit5 and GPIO is written to the output latches. If another bit of GPIO is used as a bi-directional I/O pin (i.e., bit0) and it is defined as an input at this time, the input signal present on the pin itself would be read into the CPU and rewritten to the data latch of this particular pin, overwriting the previous content. As long as the pin stays in the Input mode, no problem occurs. However, if bit0 is switched to an output, the content of the data latch may now be unknown. Reading the port register reads the values of the port pins. Writing to the port register writes the value to the port latch. When using read-modify-write instructions (i.e., BCF, BSF, etc.) on a port, the value of the port pins is read, the desired operation is done to this value, and this value is then written to the port latch.
EXAMPLE 5-1:
READ-MODIFY-WRITE INSTRUCTIONS ON AN I/O PORT
;Initial GPIO Settings ; GPIO<5:3> Inputs ; GPIO<2:0> Outputs ; ; GPIO latch GPIO pins ; ------------------BCF GPIO,5 ;pp01 -ppp pp11 pppp BCF GPIO,4 ;pp10 -ppp pp11 pppp MOVLW 007h ; TRIS GPIO ;pp10 -ppp pp10 pppp ; ;Note that the user may have expected the pin
;values to be --00 pppp. The 2nd BCF caused GP5 ;to be latched as the pin value (High).
A pin actively outputting a Low or High should not be driven from external devices at the same time, in order to change the level on this pin ("wired-or", "wired-and"). The resulting high output currents may damage the chip.
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NOTES:
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PIC16C433
6.0 LIN Bus TRANSCEIVER
The PIC16C433 has an integrated LIN bus transceiver, which allows the microcontroller to communicate via a LIN bus. The LIN bus protocol is handled by the microcontroller. The conversion from 5V signal to LIN bus signals is handled by the transceiver LIN communication. If the LINTX bit is left cleared (e.g., CLRF GPIO), no other nodes on the network will be able to communicate on the LIN Bus until LINTX is set to '1' for '0' is the dominate state for the protocol.
EXAMPLE 6-1:
MOVLW MOVWF H'C0' GPIO
Initializing LINTX and LINRX Bits
6.1
The LIN Bus Protocol
The LIN bus protocol is not described within this document. For further information regarding the LIN bus protocol, please refer to www.lin-subbus.org.
6.2
LIN Bus Interfacing
The LIN protocol is implemented and programmed by the user, using the LINTX and LINRX bits, which are used to interface to the transceiver. The LIN Bus firmware transmits by toggling the LINTX bit in the GPIO register and is read by reading the LINRX bit in the GPIO register. All aspects of the protocol are handled by software (i.e. bit-banged), where the transceiver is used as the physical interface to the LIN Bus network. For LIN Bus slave implementation software, please refer to Microchip's web site (www.microchip.com). The transceiver in the PIC16C433 uses the microcontroller's dual-die interface; therefore, the software must initialize the LINTX and LINRX bits to a '1' before each
It is recommended that the firmware verify each bit transmitted, by comparing the LINTX and LINRX bits, to ensure no bus contention or hardware failure has occurred. The LINTX and LINRX bits have no associated TRIS bits. Therefore, LINTX is always an output and LINRX is always an input.
6.3
LIN Bus Hardware Interface
Figure 6-3 shows how to implement the hardware LIN Bus interface in a master configuration and Figure 6-4 in a slave configuration using the PIC16C433. Figure 6-5 shows how to implement the hardware for a master configuration using BACT pin to generate a wake-up interrupt using GP2. The transceiver has an internal series resistor and diode, as defined in the LIN 1.2 specification, connecting VBAT and LIN pin.
FIGURE 6-1:
BLOCK DIAGRAM OF LINRX (SDA LINE)
VDD
RESET
D
Data bus
Write GPIO
ck
EN
Q
to LIN Transceiver
Output Latch
Q
D
EN ck Input Latch Read GPIO ltchpin
Schmitt Trigger
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Preliminary
DS41139B-page 33
PIC16C433
FIGURE 6-2: BLOCK DIAGRAM OF LINTX
VDD
D
Data bus
Write GPIO
ck
EN
Q
to LIN Transceiver
Q
D
EN ck
Schmitt Trigger
Read GPIO
ltchpin
6.5
Note: No resistor or diode is required between VBAT pin and 12V supply and for slave configuration.
Wake-up from SLEEP upon Bus Activity
The PIC16C433 can Wake-up from SLEEP upon bus activity in the following way: 1. Connect BACT to one of GPIO<0:3> pins. The BACT output is a CMOS-levels representation of the LIN pin. This signal can be routed to one of the GPIO<0:3> pins. The GPIO<2> external interrupt or GPIO<0:1,3> interrupt-on-change wakes up the device from SLEEP. Any one of the four GPIO pins can be used for wake-up where GPIO<2> offers multiple configuration options (Section 9.5.2) and GPIO<0:1,3> are interrupt-on-change (Section 9.5.3). Note: BACT pin is an output and must be left open if unused.
6.4
Thermal Shutdown
In thermal shutdown, the LIN bus output is disabled instantaneously. The output transistor is turned off, regardless of the input level at pin LINTX bit and only a limited current can flow into the receiver connected to the LIN bus pin. Note: TLINRX must be set to `1' at all times.
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PIC16C433
FIGURE 6-3: TYPICAL LIN BUS MASTER APPLICATION +5V +12V
VDD
PIC16C433
VBAT
BACT (2) 1k LIN Note 1 To LIN Bus
VSS
Note 1: May not be required. 2: BACT pin should be left open if not used.
FIGURE 6-4:
TYPICAL LIN BUS SLAVE APPLICATION +5V +12V
VDD
PIC16C433
VBAT
BACT (2)
LIN
To LIN Bus Note 1
VSS
Note 1: May not be required, based on bus capacitance. 2: BACT pin should be left open if not used.
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Preliminary
DS41139B-page 35
PIC16C433
FIGURE 6-5: LIN BUS APPLICATION USING WAKE-UP INTERRUPT +5V +12V
VDD
PIC16C433
VBAT
BACT GP2 LIN Note 2 1k
(1)
To LIN Bus
VSS
Note 1: For master configuration only. 2: May not be required.
TABLE 6-1:
Address 05h Name GPIO
SUMMARY OF LIN BUS TRANSCEIVER REGISTERS
Bit 7 LINTX Bit 6 LINRX Bit 5 GP5 Bit 4 GP4 Bit 3 GP3 Bit 2 GP2 Bit 1 GP1 Bit 0 GP0 Value on: POR Value on All Other RESETS
11xx xxxx 11uu uuuu
Legend: x = unknown, u = unchanged. Shaded cells not used by LIN Transceiver.
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Preliminary
2002 Microchip Technology Inc.
PIC16C433
7.0 TIMER0 MODULE
The Timer0 module timer/counter has the following features: * * * * * * 8-bit timer/counter Readable and writable 8-bit software programmable prescaler Internal or external clock select Interrupt on overflow from FFh to 00h Edge select for external clock (OPTION<4>). Clearing bit T0SE selects the rising edge. Restrictions on the external clock input are discussed in detail in Section 7.2. The prescaler is mutually exclusively shared between the Timer0 module and the Watchdog Timer. The prescaler assignment is controlled in software by control bit PSA (OPTION<3>). Clearing bit PSA will assign the prescaler to the Timer0 module. The prescaler is not readable or writable. When the prescaler is assigned to the Timer0 module, pre-scale values of 1:2, 1:4, ..., 1:256 are selectable. Section 7.3 details the operation of the prescaler.
Figure 7-1 is a simplified block diagram of the Timer0 module. Timer mode is selected by clearing bit T0CS (OPTION<5>). In Timer mode, the Timer0 module will increment every instruction cycle (without prescaler). If the TMR0 register is written, the increment is inhibited for the following two instruction cycles (Figure 7-2 and Figure 7-3). The user can work around this by writing an adjusted value to the TMR0 register. Counter mode is selected by setting bit T0CS (OPTION<5>). In Counter mode, Timer0 will increment either on every rising or falling edge of pin RA4/T0CKI. The incrementing edge is determined by the bit T0SE
7.1
Timer0 Interrupt
The TMR0 interrupt is generated when the TMR0 register overflows from FFh to 00h. This overflow sets bit T0IF (INTCON<2>). The interrupt can be masked by clearing bit T0IE (INTCON<5>). Bit T0IF must be cleared in software by the Timer0 module Interrupt Service Routine before re-enabling this interrupt. The TMR0 interrupt cannot awaken the processor from SLEEP, since the timer is shut-off during SLEEP. See Figure 7-4 for Timer0 interrupt timing.
FIGURE 7-1:
TIMER0 BLOCK DIAGRAM
Data Bus FOSC/4 0 1 1 Sync with Internal Clocks (2 TCY delay) 3 PS<2:0> TOCS PSA Set Interrupt Flag bit T0IF on Overflow TMR0 8
GP2/TOCKI/ AN2/INT TOSE
Programmable Prescaler
0
Note 1: 2:
TOCS, TOSE, PSA, PS<2:0> (OPTION<5:0>). The prescaler is shared with Watchdog Timer (refer to Figure 7-6 for detailed block diagram).
FIGURE 7-2:
PC (Program Counter) Instruction Fetch
TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALE
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PC-1 PC PC+1 PC+2 PC+3 PC+4 PC+5 PC+6
MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
TMR0 Instruction Executed
T0
T0+1
T0+2
NT0
NT0
NT0
NT0+1
NT0+2
T0
Write TMR0 executed
Read TMR0 reads NT0
Read TMR0 reads NT0
Read TMR0 reads NT0
Read TMR0 Read TMR0 reads NT0 + 1 reads NT0 + 2
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Preliminary
DS41139B-page 37
PIC16C433
FIGURE 7-3:
PC (Program Counter) Instruction Fetch TMR0 Instruction Execute T0
TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PC-1 PC PC+1 PC+2 PC+3 PC+4 PC+5 PC+6
MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
T0+1
NT0
NT0+1
Write TMR0 executed
Read TMR0 reads NT0
Read TMR0 reads NT0
Read TMR0 reads NT0
Read TMR0 reads NT0
Read TMR0 reads NT0 + 1
FIGURE 7-4:
TIMER0 INTERRUPT TIMING
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1 CLKOUT(3) Timer0 T0IF bit (INTCON<2>) GIE bit (INTCON<7>) INSTRUCTION FLOW PC Instruction Fetched Instruction Executed Note 1: 2: 3: PC Inst (PC) Inst (PC-1) PC +1 Inst (PC+1) Dummy cycle PC +1 0004h Inst (0004h) Dummy cycle 0005h Inst (0005h) Inst (0004h) FEh 1 FFh 1 Interrupt Latency(2) 00h 01h 02h
Inst (PC)
Interrupt flag bit T0IF is sampled here (every Q1). Interrupt latency = 3TCY where TCY = instruction cycle time. CLKOUT is available only in the INTRC and EXTRC oscillator modes.
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PIC16C433
7.2 Using Timer0 with an External Clock
When an external clock input is used for Timer0, it must meet certain requirements. The requirements ensure the external clock can be synchronized with the internal phase clock (TOSC). Also, there is a delay in the actual incrementing of Timer0 after synchronization. 7.2.1 EXTERNAL CLOCK SYNCHRONIZATION When a prescaler is used, the external clock input is divided by the asynchronous ripple-counter type prescaler, so that the prescaler output is symmetrical. For the external clock to meet the sampling requirement, the ripple-counter must be taken into account. Therefore, it is necessary for T0CKI to have a period of at least 4TOSC (and a small RC delay of 40 ns), divided by the prescaler value. The only requirement on T0CKI high and low time is that they do not violate the minimum pulse width requirement of 10 ns. Refer to parameters 40, 41 and 42 in the electrical specification of the desired device. 7.2.2 TMR0 INCREMENT DELAY
When no prescaler is used, the external clock input is used as the clock source. The synchronization of T0CKI with the internal phase clocks is accomplished by sampling the prescaler output on the Q2 and Q4 cycles of the internal phase clocks (Figure 7-5). Therefore, it is necessary for T0CKI to be high for at least 2TOSC (and a small RC delay of 20 ns) and low for at least 2TOSC (and a small RC delay of 20 ns). Refer to the electrical specification of the desired device.
Since the prescaler output is synchronized with the internal clocks, there is a small delay from the time the external clock edge occurs to the time the Timer0 module is actually incremented. Figure 7-5 shows the delay from the external clock edge to the timer incrementing.
FIGURE 7-5:
TIMER0 TIMING WITH EXTERNAL CLOCK
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
External Clock Input or Prescaler Output(2) (1) External Clock/Prescaler Output after Sampling Increment Timer0 (Q4) Timer0 T0 T0 + 1 (3)
Small pulse misses sampling
T0 + 2
Note 1: 2: 3:
Delay from clock input change to Timer0 increment is 3TOSC to 7TOSC (Duration of Q = TOSC). Therefore, the error in measuring the interval between two edges on Timer0 input = 4TOSC max. External clock if no prescaler selected; prescaler output otherwise. The arrows indicate the points in time where sampling occurs.
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Preliminary
DS41139B-page 39
PIC16C433
7.3 Prescaler
The PSA and PS<2:0> bits (OPTION<3:0>) determine the prescaler assignment and prescale ratio. When assigned to the Timer0 module, all instructions writing to the TMR0 register (i.e., CLRF 1, MOVWF 1, BSF 1,x...., etc.) will clear the prescaler. When assigned to WDT, a CLRWDT instruction will clear the prescaler along with the Watchdog Timer. The prescaler is not readable or writable. An 8-bit counter is available as a prescaler for the Timer0 module, or as a postscaler for the Watchdog Timer, respectively (Figure 7-6). For simplicity, this counter is being referred to as "prescaler" throughout this data sheet. Note that there is only one prescaler available which is mutually exclusively shared between the Timer0 module and the Watchdog Timer. Thus, a prescaler assignment for the Timer0 module means that there is no prescaler for the Watchdog Timer, and vice-versa.
FIGURE 7-6:
BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
Data Bus 8 1 0 M U X SYNC 2 Cycles TMR0 reg
CLKOUT (= FOSC/4)
0 GP2/T0CKI/ AN2/INT T0SE 1
M U X
T0CS
PSA
Set Flag bit T0IF on Overflow
0 M U X
8-bit Prescaler 8 8 - to - 1MUX PS<2:0>
Watchdog Timer
1
PSA 0 MUX 1 PSA
WDT Enable bit
WDT Timeout Note: T0CS, T0SE, PSA, PS<2:0> are (OPTION<5:0>).
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Preliminary
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PIC16C433
7.3.1 SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software control (i.e., it can be changed "on-the-fly" during program execution). Note: To avoid an unintended device RESET, the following instruction sequence (shown in Example 7-1) must be executed when changing the prescaler assignment from Timer0 to the WDT. This sequence must be followed even if the WDT is disabled. To change prescaler from the WDT to the Timer0 module, use the sequence shown in Example 7-2.
EXAMPLE 7-2:
CLRWDT BSF MOVLW MOVWF BCF
CHANGING PRESCALER (WDT TIMER0)
;Clear WDT and ;prescaler ;Bank 1 ;Select TMR0, new ;prescale value and ;clock source ;Bank 0
STATUS, RP0 b'xxxx0xxx' OPTION_REG STATUS, RP0
EXAMPLE 7-1:
BCF CLRF BSF CLRWDT MOVLW MOVWF BCF
Changing Prescaler (Timer0 WDT)
;Bank 0 ;Clear TMR0 & Prescaler ;Bank 1 ;Clears WDT ;Select new prescale ;value & WDT ;Bank 0
STATUS, RP0 TMR0 STATUS, RP0 b'xxxx1xxx' OPTION_REG STATUS, RP0
TABLE 7-1:
Address Name 01h 0Bh/8Bh 81h 85h TMR0
REGISTERS ASSOCIATED WITH TIMER0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR xxxx xxxx INTE T0SE TRIS4 GPIE PSA TRIS3 T0IF PS2 TRIS2 INTF PS1 TRIS1 GPIF PS0 TRIS0 0000 000x 1111 1111 --11 1111 Value on all other RESETS uuuu uuuu 0000 000u 1111 1111 --11 1111
Timer0 Module's Register GIE PEIE T0IE T0CS TRIS5
INTCON
OPTION GPPU INTEDG TRIS -- --
Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by Timer0.
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Preliminary
DS41139B-page 41
PIC16C433
NOTES:
DS41139B-page 42
Preliminary
2002 Microchip Technology Inc.
PIC16C433
8.0 ANALOG-TO-DIGITAL CONVERTER (A/D) MODULE
The Analog-to-Digital (A/D) converter module has four analog inputs. The A/D allows conversion of an analog input signal to a corresponding 8-bit digital number (refer to Application Note AN546 for use of A/D Converter). The output of the sample and hold is the input into the converter, which generates the result via successive approximation. The analog reference voltage is software selectable to either the device's positive supply voltage (VDD), or the voltage level on the GP1/AN1/VREF pin. The A/D converter has a unique feature of being able to operate while the device is in SLEEP mode. The A/D module has three registers. These registers are: * * * A/D Result Register (ADRES) A/D Control Register 0 (ADCON0) A/D Control Register 1 (ADCON1) The ADCON0 Register, shown in Figure 8-1, controls the operation of the A/D module. The ADCON1 Register, shown in Figure 8-2, configures the functions of the port pins. The port pins can be configured as analog inputs (GP1 can also be a voltage reference) or as digital I/O. Note 1: If the port pins are configured as analog inputs (RESET condition), reading the port (MOVF GPIO,W) results in reading '0's. 2: Changing ADCON1 Register can cause the GPIF and INTF flags to be set in the INTCON Register. These interrupts should be disabled prior to modifying ADCON1.
REGISTER 8-1: ADCON0 REGISTER (ADDRESS 1Fh)
R/W-0 ADCS1 bit7 bit 7-6 ADCS<1:0>: A/D Conversion Clock Select bits 00 = FOSC/2 01 = FOSC/8 10 = FOSC/32 11 = FRC (clock derived from an RC oscillation) Reserved CHS<1:0>: Analog Channel Select bits 00 = channel 0, (GP0/AN0) 01 = channel 1, (GP1/AN1) 10 = channel 2, (GP2/AN2) 11 = channel 3, (GP4/AN3) GO/DONE: A/D Conversion Status bit If ADON = 1: 1 = A/D conversion in progress (setting this bit starts the A/D conversion) 0 = A/D conversion not in progress (this bit is automatically cleared by hardware when the A/D conversion is complete) bit 1 bit 0 Reserved ADON: A/D On bit 1 = A/D converter module is operating 0 = A/D converter module is shut-off and consumes no operating current Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown R/W-0 ADCS0 R/W-0 reserved R/W-0 CHS1 R/W-0 CHS0 R/W-0 GO/DONE R/W-0 reserved R/W-0 ADON bit0
bit 5 bit 4-3
bit 2
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Preliminary
DS41139B-page 43
PIC16C433
REGISTER 8-2: ADCON1 REGISTER (ADDRESS 9Fh
U-0 -- bit7 bit 7-2 bit 1-0 Unimplemented: Read as `0' PCFG<2:0>: A/D Port Configuration Control bits PCFG<2:0> 000 001 010 011 100 101 110 111
(1)
U-0 --
U-0 --
U-0 --
U-0 --
R/W-0 PCFG2
R/W-0 PCFG1
R/W-0 PCFG0 bit0
GP4 A A D D D D D D
GP2 A A A A D D D D
GP1 A VREF A VREF A VREF D D
GP0 A A A A A A A D
VREF VDD GP1 VDD GP1 VDD GP1 VDD VDD
A = Analog Input D = Digital I/O Note 1: Value on RESET. 2: Any instruction that reads a pin configured as an analog input will read a '0'.
Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown
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PIC16C433
The ADRES Register contains the result of the A/D conversion. When the A/D conversion is complete, the result is loaded into the ADRES register, the GO/DONE bit (ADCON0<2>) is cleared and A/D interrupt flag bit ADIF (PIE1<6>) is set. The block diagrams of the A/D module are shown in Figure 8-1. After the A/D module has been configured as desired, the selected channel must be acquired before the conversion is started. The analog input channels must have their corresponding TRIS bits selected as an input. To determine sample time, see Section 8.1. After this acquisition time has elapsed, the A/D conversion can be started. The following steps should be followed for doing an A/D conversion: 1. Configure the A/D module: * Configure analog pins/voltage reference/ and digital I/O (ADCON1 and TRIS) * Select A/D input channel (ADCON0) * Select A/D conversion clock (ADCON0) * Turn on A/D module (ADCON0) 2. Configure A/D interrupt (if desired): * Clear ADIF bit * Set ADIE bit * Set GIE bit Wait the required acquisition time. Start conversion: * Set GO/DONE bit (ADCON0) Wait for A/D conversion to complete, by either: * Polling for the GO/DONE bit to be cleared OR 6. 7. * Waiting for the A/D interrupt Read A/D Result Register (ADRES), clear bit ADIF if required. For the next conversion, go to step 1, step 2, or step 3, as required. The A/D conversion time per bit is defined as TAD. A minimum wait of 2TAD is required before next acquisition starts.
3. 4. 5.
FIGURE 8-1:
A/D BLOCK DIAGRAM
CHS<1:0>
11 VIN (Input Voltage) 10 GP2/AN2 01 GP1/AN1/VREF 00 VDD VREF (Reference Voltage) PCFG<2:0> GP0/AN0 GP4/AN3
A/D Converter
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Preliminary
DS41139B-page 45
PIC16C433
8.1 A/D Sampling Requirements
For the A/D converter to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The analog input model is shown in Figure 8-2. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD), see Figure 8-2. The maximum recommended impedance for analog sources is 10 k. After the analog input channel is selected (changed), this acquisition must be done before the conversion can be started. To calculate the minimum acquisition time, Equation 8-1 may be used. This equation assumes that 1/2 LSb error is used (512 steps for the A/D). The 1/2 LSb error is the maximum error allowed for the A/D to meet its specified resolution. Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out. 2: The charge holding capacitor (CHOLD) is not discharged after each conversion. 3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin leakage specification. 4: After a conversion has completed, a 2.0 TAD delay must complete before acquisition can begin again. During this time, the holding capacitor is not connected to the selected A/D input channel.
EXAMPLE 8-1:
CALCULATING THE MINIMUM REQUIRED SAMPLE TIME
EQUATION 8-1:
A/D MINIMUM CHARGING TIME
(-Tc/CHOLD(RIC + RSS + RS))
TACQ = Internal Amplifier Settling Time + Holding Capacitor Charging Time + Temperature Coefficient TACQ = 5 s + Tc + [(Temp - 25C)(0.05 s/C)] TC = -CHOLD (RIC + RSS + RS) ln(1/512) -51.2 pF (1 k + 7 k + 10 k) ln(0.0020) -51.2 pF (18 k) ln(0.0020) -0.921 s (-6.2146) 5.724 s TACQ = 5 s + 5.724 s + [(50C - 25C)(0.05 s/C)] 10.724 s + 1.25 s 11.974 s
VHOLD = (VREF - (VREF/512)) * (1 - e or
)
Tc = -(51.2 pF)(1 k + RSS + RS) ln(1/511)
Example 8-1 shows the calculation of the minimum required acquisition time TACQ. This calculation is based on the following system assumptions. Rs = 10 k 1/2 LSb error VDD = 5V Rss = 7 k Temperature (system max.) = 50C VHOLD = 0 @ t = 0
FIGURE 8-2:
ANALOG INPUT MODEL
VDD VT = 0.6V RIC 1k Sampling Switch SS RSS CHOLD = DAC capacitance = 51.2 pF VSS Legend: CPIN = input capacitance = threshold voltage VT I leakage = leakage current at the pin due to various junctions RIC = interconnect resistance SS = sampling switch CHOLD = sample/hold capacitance (from DAC)
RS
RAX
VA
CPIN 5 pF
VT = 0.6V
I leakage 500 nA
6V 5V VDD 4V 3V 2V
5 6 7 8 9 10 11 Sampling Switch (k)
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PIC16C433
8.2 Selecting the A/D Conversion Clock 8.3 Configuring Analog Port Pins
The A/D conversion time per bit is defined as TAD. The A/D conversion requires 9.5 TAD per 8-bit conversion. The source of the A/D conversion clock is software selected. The four possible options for TAD are: * * * * 2TOSC 8TOSC 32TOSC Internal ADC RC oscillator The ADCON1 and TRIS Registers control the operation of the A/D port pins. The port pins that are desired as analog inputs must have their corresponding TRIS bits set (input). If the TRIS bit is cleared (output), the digital output level (VOH or VOL) will be converted. The A/D operation is independent of the state of the CHS<2:0> bits and the TRIS bits. Note 1: When reading the port register, all pins configured as analog input channel will read as cleared (a low level). Pins configured as digital inputs, will convert an analog input. Analog levels on a digitally configured input will not affect the conversion accuracy. 2: Analog levels on any pin that is defined as a digital input (including the AN<3:0> pins) may cause the input buffer to consume current that is out of the devices specification.
For correct A/D conversions, the A/D conversion clock (TAD) must be selected to ensure a minimum TAD time of 1.6 s. If the minimum TAD time of 1.6 s can not be obtained, TAD should be 8 s for preferred operation. Table 8-1 shows the resultant TAD times derived from the device operating frequencies and the A/D clock source selected.
TABLE 8-1:
TAD vs. DEVICE OPERATING FREQUENCIES
AD Clock Source (TAD) Device Frequency 4 MHz ns(2) 1.25 MHz 333.33 kHz
Operation
ADCS<1:0>
2TOSC 00 500 1.6 s 6 s 8TOSC 01 2.0 s 6.4 s 24 s(3) (3) 32TOSC 10 8.0 s 25.6 s 96 s(3) (5) (1,4) (1,4) Internal ADC RC Oscillator 11 2 - 6 s 2 - 6 s 2 - 6 s(1) Note 1: The RC source has a typical TAD time of 4 s. 2: These values violate the minimum required TAD time. 3: For faster conversion times, the selection of another clock source is recommended. 4: While in RC mode, with device frequency above 1 MHz, conversion accuracy is out of specification. 5: For extended voltage devices (LC), please refer to Section 12.0, Electrical Specifications.
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Preliminary
DS41139B-page 47
PIC16C433
8.4 A/D Conversions
Example 8-2 shows how to perform an A/D conversion. The GPIO pins are configured as analog inputs. The analog reference (VREF) is the device VDD. The A/D interrupt is enabled and the A/D conversion clock is FRC. The conversion is performed on the GP0 channel. Note: The GO/DONE bit should NOT be set in the same instruction that turns on the A/D. Clearing the GO/DONE bit during a conversion will abort the current conversion. The ADRES register will NOT be updated with the partially completed A/D conversion sample. That is, the ADRES register will continue to contain the value of the last completed conversion (or the last value written to the ADRES register). After the A/D conversion is aborted, a 2TAD wait is required before the next acquisition is started. After this 2TAD wait, an acquisition is automatically started on the selected channel.
EXAMPLE 8-2:
BSF CLRF BSF BCF MOVLW MOVWF BCF BSF BSF ; ; ; ;
DOING AN A/D CONVERSION
RP0 ADIE RP0 ; ; ; ; ; ; ; ; ; Select Page 1 Configure A/D inputs Enable A/D interrupts Select Page 0 RC Clock, A/D is on, Channel 0 is selected Clear A/D interrupt flag bit Enable peripheral interrupts Enable all interrupts
STATUS, ADCON1 PIE1, STATUS, 0xC1 ADCON0 PIR1, INTCON, INTCON,
ADIF PEIE GIE
Ensure that the required sampling time for the selected input channel has elapsed. Then the conversion may be started. BSF : : ADCON0, GO ; Start A/D Conversion ; The ADIF bit will be set and the GO/DONE bit ; is cleared upon completion of the A/D Conversion.
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PIC16C433
8.5 A/D Operation During SLEEP 8.7 Effects of a RESET
The A/D module can operate during SLEEP mode. This requires that the A/D clock source be set to RC (ADCS<1:0> = 11). When the RC clock source is selected, the A/D module waits one instruction cycle before starting the conversion. This allows the SLEEP instruction to be executed, which eliminates all digital switching noise from the conversion. When the conversion is completed, the GO/DONE bit will be cleared, and the result loaded into the ADRES Register. If the A/ D interrupt is enabled, the device will wake-up from SLEEP. If the A/D interrupt is not enabled, the A/D module will then be turned off, although the ADON bit will remain set. When the A/D clock source is another clock option (not RC), a SLEEP instruction will cause the present conversion to be aborted and the A/D module to be turned off, though the ADON bit will remain set. Turning off the A/D places the A/D module in its lowest current consumption state. Note: For the A/D module to operate in SLEEP, the A/D clock source must be set to RC (ADCS<1:0> = 11). To perform an A/D conversion in SLEEP, the GO/DONE bit must be set, followed by the SLEEP instruction. A device RESET forces all registers to their RESET state. This forces the A/D module to be turned off, and any conversion is aborted. The value that is in the ADRES register is not modified for a RESET. The ADRES register will contain unknown data after a Power-on Reset.
8.8
Connection Considerations
If the input voltage exceeds the rail values (VSS or VDD) by greater than 0.2V, then the accuracy of the conversion is out of specification. Note: For the PIC16C433, care must be taken when using the GP4 pin in A/D conversions due to its proximity to the OSC1 pin.
An external RC filter is sometimes added for antialiasing of the input signal. The R component should be selected to ensure that the total source impedance is kept under the 10 k recommended specification. Any external components connected (via hi-impedance) to an analog input pin (capacitor, zener diode, etc.) should have very little leakage current at the pin.
8.9
Transfer Function
8.6
A/D Accuracy/Error
Digital Code Output
The overall accuracy of the A/D is less than 1 LSb for VDD = 5V 10% and the analog VREF = VDD. This overall accuracy includes offset error, full scale error and integral error. The A/D converter is monotonic over the full VDD range. The resolution and accuracy may be less when either the analog reference (VDD) is less than 5.0V, or when the analog reference (VREF) is less than VDD. The maximum pin leakage current is specified in the Device Data Sheet electrical specification, parameter #D060. In systems where the device frequency is low, use of the A/D RC clock is preferred. At moderate to high frequencies, TAD should be derived from the device oscillator. TAD must not violate the minimum and should be 8 s for preferred operation. This is because TAD, when derived from TOSC, is kept away from on-chip phase clock transitions. This reduces, to a large extent, the effects of digital switching noise. This is not possible with the RC derived clock. The loss of accuracy due to digital switching noise can be significant if many I/O pins are active. In systems where the device will enter SLEEP mode after the start of the A/D conversion, the RC clock source selection is required. In this mode, the digital noise from the modules in SLEEP is stopped. This method gives high accuracy.
The ideal transfer function of the A/D converter is as follows: the first transition occurs when the analog input voltage (VAIN) is 1 LSb (or Analog VREF/256) (Figure 83).
FIGURE 8-3:
A/D TRANSFER FUNCTION
FFh FEh
04h 03h 02h 01h 00h 256 LSb (full scale) 255 LSb 0.5 LSb 1 LSb 2 LSb 3 LSb 4 LSb
Analog Input Voltage
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Preliminary
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PIC16C433
FIGURE 8-4: FLOW CHART OF A/D OPERATION
ADON = 0
Yes ADON = 0? No Acquire Selected Channel
Yes GO = 0? No Yes Start of A/D Conversion Delayed 1 Instruction Cycle SLEEP Yes Instruction? No
A/D Clock = RC? No
Finish Conversion GO = 0 ADIF = 1
Device in SLEEP? No
Yes
Abort Conversion GO = 0 ADIF = 0
Finish Conversion GO = 0 ADIF = 1
Wake-up Yes from SLEEP? No
Wait 2 TAD
Finish Conversion GO = 0 ADIF = 1
SLEEP Power-down A/D
Wait 2 TAD
Stay in SLEEP Power-down A/D
Wait 2 TAD
TABLE 8-2:
Address Name 0Bh/8Bh 0Ch 8Ch 1Eh 1Fh 9Fh 05h 85h
SUMMARY OF A/D REGISTERS
Bit 7 GIE -- -- Bit 6 PEIE ADIF ADIE Bit 5 T0IE -- -- Bit 4 INTE -- -- Bit 3 GPIE -- -- Bit 2 T0IF -- -- Bit 1 INTF -- -- Bit 0 GPIF -- -- Value on Power-on Reset 0000 000x -0-- ----0-- ---xxxx xxxx CHS0 -- GP3 GO/DONE PCFG2 GP2 TRIS2 reserved PCFG1 GP1 TRIS1 ADON PCFG0 GP0 TRIS0 0000 0000 ---- -000 11xx xxxx --11 1111 Value on all other RESETS 0000 000u -0-- ----0-- ---uuuu uuuu 0000 0000 ---- -000 11uu uuuu --11 1111
INTCON(1) PIR1 PIE1 ADRES ADCON0 ADCON1 GPIO TRIS
A/D Result Register ADCS1 ADCS0 reserved CHS1 -- LINTX -- -- LINRX -- -- GP5 TRIS5 -- GP4
TRIS4 TRIS3
Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used for A/D conversion. Note 1: These registers can be addressed from either bank.
DS41139B-page 50
Preliminary
2002 Microchip Technology Inc.
PIC16C433
9.0 SPECIAL FEATURES OF THE CPU
What sets a microcontroller apart from other processors are special circuits to deal with the needs of realtime applications. The PIC16C433 device has a host of such features intended to maximize system reliability, minimize cost through elimination of external components, provide power saving operating modes and offer code protection. These are: * Oscillator Selection * RESET - Power-on Reset (POR) - Power-up Timer (PWRT) - Oscillator Start-up Timer (OST) * Interrupts * Watchdog Timer (WDT) * SLEEP * Code Protection * ID Locations * In-Circuit Serial Programming The PIC16C433 has a Watchdog Timer, which can be shut-off only through configuration bits. It runs off its own RC oscillator for added reliability. There are two timers that offer necessary delays on power-up. One is the Oscillator Start-up Timer (OST), intended to keep the chip in RESET until the crystal oscillator is stable. The other is the Power-up Timer (PWRT), which provides a fixed delay of 72 ms (nominal) on power-up only, designed to keep the part in RESET while the power supply stabilizes. With these two timers on-chip, most applications need no external RESET circuitry. SLEEP mode is designed to offer a very low current Power-down mode. The user can wake-up from SLEEP through external RESET, Watchdog Timer wake-up, or through an interrupt. Several oscillator options are also made available to allow the part to fit the application. The INTRC/EXTRC oscillator option saves system cost, while the LP crystal option saves power. A set of configuration bits is used to select various options.
9.1
Configuration Bits
The configuration bits can be programmed (read as '0'), or left unprogrammed (read as '1'), to select various device configurations. These bits are mapped in program memory location 2007h. The user will note that address 2007h is beyond the user program memory space. In fact, it belongs to the special test/configuration memory space (2000h3FFFh), which can be accessed only during programming.
REGISTER 9-1:
CP bit13 CP
CONFIG -- CONFIGURATION WORD (ADDRESS: 2007H)
BORV1 BORV0 CP CP -- BODEN MCLRE PWRTE WDTE FOSC2 FOSC1 FOSC0 bit0
bit 13-8, 6-5:
CP<1:0>: Code Protection bit pairs(1)
11 = Code protection off 10 = Locations 400h through 7FEh code protected 01 = Locations 200h through 7FEh code protected 00 = All memory is code protected
bit 7:
MCLRE: Master Clear Reset Enable bit
1 = Master Clear enabled 0 = Master Clear disabled
bit 4:
PWRTE: Power-up Timer Enable bit
1 = PWRT disabled 0 = PWRT enabled
bit 3:
WDTE: Watchdog Timer Enable bit
1 = WDT enabled 0 = WDT disabled
bit 2-0:
FOSC<2:0>: Oscillator Selection bits
111 = EXTRC, clockout on OSC2 110 = EXTRC, OSC2 is I/O 101 = INTRC, clockout on OSC2 100 = INTRC, OSC2 is I/O 011 = Invalid selection 010 = HS oscillator 001 = XT oscillator 000 = LP oscillator
Note: Legend
All of the CP<1:0> pairs have to be given the same value to enable the code protection scheme listed.
R = Readable bit -n = Value at POR
W = Writable bit 1 = bit is set
U = Unimplemented bit, read as `0' 0 = bit is cleared x = bit is unknown
2002 Microchip Technology Inc.
Preliminary
DS41139B-page 51
PIC16C433
9.2
9.2.1
Oscillator Configurations
OSCILLATOR TYPES
TABLE 9-1:
CAPACITOR SELECTION FOR CERAMIC RESONATORS - PIC16C433
Cap. Range C1 Cap. Range C2
The PIC16C433 can be operated in seven different oscillator modes. The user can program three configuration bits (FOSC<2:0>) to select one of these seven modes: * * * * * LP: HS: XT: INTRC*: EXTRC*: Low Power Crystal High Speed Crystal/Resonator Crystal/Resonator Internal 4 MHz Oscillator External Resistor/Capacitor
Osc Type XT
Resonator Freq
*Can be configured to support CLKOUT 9.2.2 CRYSTAL OSCILLATOR/CERAMIC RESONATORS
455 kHz 22-100 pF 22-100 pF 2.0 MHz 15-68 pF 15-68 pF 4.0 MHz 15-68 pF 15-68 pF HS 4.0 MHz 15-68 pF 15-68 pF 8.0 MHz 10-68 pF 10-68 pF 10.0 MHz 10-22 pF 10-22 pF These values are for design guidance only. Since each resonator has its own characteristics, the user should consult the resonator manufacturer for appropriate values of external components.
In XT, HS or LP modes, a crystal or ceramic resonator is connected to the GP5/OSC1/CLKIN and GP4/OSC2 pins to establish oscillation (Figure 9-1). The PIC16C433 oscillator design requires the use of a parallel cut crystal. Use of a series cut crystal may give a frequency out of the crystal manufacturers specifications. When in XT, HS or LP modes, the device can have an external clock source drive the GP5/OSC1/ CLKIN pin (Figure 9-2).
TABLE 9-2:
CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR PIC16C433
Cap. Range C1 Cap. Range C2
Osc Type LP
Resonator Freq
FIGURE 9-1:
CRYSTAL OPERATION OR CERAMIC RESONATOR (XT, HS OR LP OSC CONFIGURATION)
OSC1 SLEEP XTAL RF(3) OSC2 To Internal Logic
C1(1)
C2(1) Note 1:
RS(2)
See Capacitor Selection tables for recommended values of C1 and C2. 2: A series resistor (RS) may be required for AT strip cut crystals. 3: RF varies with the Oscillator mode selected (approx. value = 10 M).
32 kHz(1) 15 pF 15 pF 100 kHz 15-30 pF 30-47 pF 200 kHz 15-30 pF 15-82 pF XT 100 kHz 15-30 pF 200-300 pF 200 kHz 15-30 pF 100-200 pF 455 kHz 15-30 pF 15-100 pF 1 MHz 15-30 pF 15-30 pF 2 MHz 15-30 pF 15-30 pF 4 MHz 15-47 pF 15-47 pF HS 4 MHz 15-30 pF 15-30 pF 8 MHz 15-30 pF 15-30 pF 10 MHz 15-30 pF 15-30 pF Note 1: For VDD > 4.5V, C1 = C2 30 pF is recommended. These values are for design guidance only. RS may be required in HS mode, as well as XT mode, to avoid overdriving crystals with low drive level specification. Since each crystal has its own characteristics, the user should consult the crystal manufacturer for appropriate values of external components.
FIGURE 9-2:
EXTERNAL CLOCK INPUT OPERATION (XT, HS OR LP OSC CONFIGURATION)
OSC1
Clock from ext. system Open
OSC2
DS41139B-page 52
Preliminary
2002 Microchip Technology Inc.
PIC16C433
9.2.3 EXTERNAL CRYSTAL OSCILLATOR CIRCUIT 9.2.4 EXTERNAL RC OSCILLATOR Either a pre-packaged oscillator, or a simple oscillator circuit with TTL gates, can be used as an external crystal oscillator circuit. Pre-packaged oscillators provide a wide operating range and better stability. A well designed crystal oscillator will provide good performance with TTL gates. Two types of crystal oscillator circuits can be used; one with parallel resonance, or one with series resonance.PIC16C433 Figure 9-3 shows implementation of a parallel resonant oscillator circuit. The circuit is designed to use the fundamental frequency of the crystal. The 74AS04 inverter performs the 180-degree phase shift that a parallel oscillator requires. The 4.7 k resistor provides the negative feedback for stability. The 10 k potentiometers bias the 74AS04 in the linear region. This circuit could be used for external oscillator designs. For timing insensitive applications, the RC device option offers additional cost savings. The RC oscillator frequency is a function of the supply voltage, the resistor (REXT) and capacitor (CEXT) values, and the operating temperature. In addition to this, the oscillator frequency will vary from unit to unit, due to normal process parameter variation. Furthermore, the difference in lead frame capacitance between package types will also affect the oscillation frequency, especially for low CEXT values. The user also needs to take into account variation due to tolerance of external R and C components used. Figure 9-5 shows how the R/C combination is connected to the PIC16C433. For REXT values below 2.2 k, the oscillator operation may become unstable or stop completely. For very high REXT values (i.e., 1 M), the oscillator becomes sensitive to noise, humidity and leakage. Thus, we recommend keeping REXT between 3 k and 100 k. Although the oscillator will operate with no external capacitor (CEXT = 0 pF), we recommend using values above 20 pF for noise and stability reasons. With no or small external capacitance, the oscillation frequency can vary dramatically due to changes in external capacitances, such as PCB trace capacitance or package lead frame capacitance. The variation is greater for larger R (since leakage current variation will affect RC frequency more for large R) and for smaller C (since variation of input capacitance will affect RC frequency more).
FIGURE 9-3:
EXTERNAL PARALLEL RESONANT CRYSTAL OSCILLATOR CIRCUIT
To Other Devices
+5V 10k 4.7k 74AS04 74AS04 PIC16C433 CLKIN
10k XTAL 10k 20 pF 20 pF
FIGURE 9-5:
VDD REXT
EXTERNAL RC OSCILLATOR MODE
Figure 9-4 shows a series resonant oscillator circuit. This circuit is also designed to use the fundamental frequency of the crystal. The inverter performs a 180degree phase shift in a series resonant oscillator circuit. The 330 resistors provide the negative feedback to bias the inverters in their linear region.
OSC1
Internal Clock
CEXT VSS FOSC/4
N PIC16C433
FIGURE 9-4:
EXTERNAL SERIES RESONANT CRYSTAL OSCILLATOR CIRCUIT
330 74AS04 To Other Devices 74AS04 PIC16C433 CLKIN
OSC2/CLKOUT
330 74AS04 0.1 F XTAL
2002 Microchip Technology Inc.
Preliminary
DS41139B-page 53
PIC16C433
9.2.5 INTERNAL 4 MHz RC OSCILLATOR
9.3
RESET
The internal RC oscillator provides a fixed 4 MHz (nominal) system clock at VDD = 5V and 25C. See Section 13.0 for information on variation over voltage and temperature. In addition, a calibration instruction is programmed into the last address of the program memory, which contains the calibration value for the internal RC oscillator. This value is programmed as a RETLW XX instruction, where XX is the calibration value. In order to retrieve the calibration value, issue a CALL YY instruction, where YY is the last location in program memory. Control will be returned to the user's program with the calibration value loaded into the W register. The program should then perform a MOVWF OSCCAL instruction to load the value into the internal RC oscillator trim register. OSCCAL, when written to with the calibration value, will "trim" the internal oscillator to remove process variation from the oscillator frequency. Bits <7:4>, CAL<3:0> are used for fine calibration, while bit3, CALFST, and bit2, CALSLW, are used for more coarse adjustment. Adjusting CAL<3:0> from 0000 to 1111 yields a higher clock speed. Set CALFST = 1 for greater increase in frequency, or set CALSLW = 1 for greater decrease in frequency. Note that bits 1 and 0 of OSCCAL are unimplemented and should be written as 0, when modifying OSCCAL for compatibility with future devices. Note: Please note that erasing the device will also erase the pre-programmed internal calibration value for the internal oscillator. The calibration value must be saved prior to erasing the part. CLKOUT
The PIC16C433 differentiates between various kinds of RESET: * * * * Power-on Reset (POR) MCLR Reset during normal operation MCLR Reset during SLEEP WDT Reset (normal operation)
Some registers are not affected in any RESET condition; their status is unknown on POR and unchanged in any other RESET. Most other registers are reset to a "RESET state" on Power-on Reset (POR), MCLR Reset, WDT Reset, and MCLR Reset during SLEEP. They are not affected by a WDT wake-up, which is viewed as the resumption of normal operation. The TO and PD bits are set or cleared differently in different RESET situations, as indicated in Table 9-5. These bits are used in software to determine the nature of the RESET. See Table 9-6 for a full description of RESET states of all registers. A simplified block diagram of the On-Chip Reset circuit is shown in Figure 9-6. The PIC16C433 has a MCLR noise filter in the MCLR Reset path. The filter will detect and ignore small pulses. It should be noted that a WDT Reset does not drive MCLR pin low. When MCLR is asserted, the state of the OSC1/CLKIN and CLKOUT/OSC2 pins are as follows:
TABLE 9-3:
CLKIN/CLKOUT PIN STATES WHEN MCLR ASSERTED
OSC1/CLKIN Pin OSC1 pin is tri-stated and driven by external circuit OSC1 pin is tri-stated and driven by external circuit OSC1 pin is tri-state input OSC1 pin is tri-state input OSC2/CLKOUT Pin OSC2 pin is driven low
9.2.6
Oscillator Mode EXTRC, CLKOUT on OSC2
The PIC16C433 can be configured to provide a clock out signal (CLKOUT) on pin 3, when the configuration word address (2007h) is programmed with FOSC2, FOSC1, and FOSC0, equal to 101 for INTRC or 111 for EXTRC. The oscillator frequency, divided by 4, can be used for test purposes or to synchronize other logic.
EXTRC, OSC2 is I/O
OSC2 pin is tri-state input
INTRC, CLKOUT on OSC2 INTRC, OSC2 is I/O
OSC2 pin is driven low OSC2 pin is tri-state input
DS41139B-page 54
Preliminary
2002 Microchip Technology Inc.
PIC16C433
FIGURE 9-6: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
Weak Pull-up
GP3/MCLR/VPP pin
MCLRE Internal MCLR WDT SLEEP Module WDT Timeout VDD Rise Detect Power-on Reset
VDD S OST/PWRT OST 10-bit Ripple-counter OSC1/ CLKIN pin On-chip(1) RC OSC Chip_Reset R Q
PWRT 10-bit Ripple-counter
Enable PWRT Enable OST
See Table 9-4 for timeout situations.
Note 1:
This is a separate oscillator from the RC oscillator of the CLKIN pin.
2002 Microchip Technology Inc.
Preliminary
DS41139B-page 55
PIC16C433
9.4 Power-on Reset (POR), Power-up Timer (PWRT) and Oscillator Start-up Timer (OST)
POWER-ON RESET (POR) 9.4.3 OSCILLATOR START-UP TIMER (OST) The Oscillator Start-up Timer (OST) provides 1024 oscillator cycle (from OSC1 input) delay after the PWRT delay is over. This ensures that the crystal oscillator, or resonator has started and stabilized. The OST timeout is invoked only for XT, LP and HS modes and only on Power-on Reset or wake-up from SLEEP. 9.4.4 TIMEOUT SEQUENCE
9.4.1
The on-chip POR circuit holds the chip in RESET until VDD has reached a high enough level for proper operation. To take advantage of the POR, just tie the MCLR pin through a resistor to VDD. This will eliminate external RC components usually needed to create a Poweron Reset. A maximum rise time for VDD is specified. See Electrical Specifications for details. When the device starts normal operation (exits the RESET condition), device operating parameters (voltage, frequency, temperature, ...) must be met to ensure operation. If these conditions are not met, the device must be held in RESET until the operating conditions are met. For additional information, refer to Application Note AN607, "Power-up Trouble Shooting." 9.4.2 POWER-UP TIMER (PWRT)
On power-up, the timeout Sequence is as follows: first, PWRT timeout is invoked after the POR time delay has expired; then, OST is activated. The total timeout will vary, based on oscillator configuration and the status of the PWRT. For example, in RC mode with the PWRT disabled, there will be no timeout at all. Figure 9-7, Figure 9-8, and Figure 9-9 depict timeout sequences on power-up. Since the timeouts occur from the POR pulse, if MCLR is kept low long enough, the timeouts will expire. Then bringing MCLR high will begin execution immediately (Figure 9-9). This is useful for testing purposes, or to synchronize more than one PIC16C433 device operating in parallel. 9.4.5 POWER CONTROL/STATUS REGISTER (PCON)
The Power-up Timer provides a fixed 72 ms nominal timeout on power-up only, from the POR. The Powerup Timer operates on an internal RC oscillator. The chip is kept in RESET as long as the PWRT is active. The PWRT's time delay allows VDD to rise to an acceptable level. A configuration bit is provided to enable/disable the PWRT. The power-up time delay will vary from chip to chip due to VDD, temperature and process variation.
The Power Control/Status Register, PCON (address 8Eh), has one bit. Bit1 is POR (Power-on Reset). It is cleared on a Poweron Reset and is unaffected otherwise. The user sets this bit following a Power-on Reset. On subsequent RESETS, if POR is `0', it will indicate that a Power-on Reset must have occurred.
TABLE 9-4:
TIMEOUT IN VARIOUS SITUATIONS
Power-up PWRTE = 0 72 ms + 1024TOSC 72 ms PWRTE = 1 1024TOSC -- Wake-up from SLEEP 1024TOSC --
Oscillator Configuration XT, HS, LP INTRC, EXTRC
TABLE 9-5:
POR
STATUS/PCON BITS AND THEIR SIGNIFICANCE
TO PD
0 1 1 Power-on Reset 0 0 x Illegal, TO is set on POR 0 x 0 Illegal, PD is set on POR 1 0 u WDT Reset 1 0 0 WDT Wake-up 1 u u MCLR Reset during normal operation 1 1 0 MCLR Reset during SLEEP or interrupt Wake-up from SLEEP Legend: u = unchanged, x = unknown
DS41139B-page 56
Preliminary
2002 Microchip Technology Inc.
PIC16C433
TABLE 9-6: RESET CONDITION FOR SPECIAL REGISTERS
Condition Power-on Reset MCLR Reset during normal operation MCLR Reset during SLEEP WDT Reset during normal operation WDT Wake-up from SLEEP Interrupt Wake-up from SLEEP Program Counter 000h 000h 000h 000h PC + 1 PC + 1(1) STATUS Register 0001 1xxx 000u uuuu 0001 0uuu 0000 uuuu uuu0 0uuu uuu1 0uuu PCON Register ---- --0---- --u---- --u---- --u---- --u---- --u-
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0' Note 1: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h).
TABLE 9-7:
Register W INDF TMR0 PCL STATUS FSR GPIO PCLATH INTCON PIR1 ADCON0 OPTION TRIS PIE1 PCON OSCCAL ADCON1
INITIALIZATION CONDITIONS FOR ALL REGISTERS
Power-on Reset xxxx xxxx 0000 0000 xxxx xxxx 0000 0000 0001 1xxx xxxx xxxx 11xx xxxx ---0 0000 0000 000x -0-- ---0000 0000 1111 1111 --11 1111 -0-- ------- --00111 00----- -000 MCLR Reset WDT Reset uuuu uuuu 0000 0000 uuuu uuuu 0000 0000 000q quuu(3) uuuu uuuu 11uu uuuu ---0 0000 0000 000u -0-- ---0000 0000 1111 1111 --11 1111 -0-- ------- --uuuuu uu----- -000 Wake-up via WDT or Interrupt uuuu uuuu 0000 0000 uuuu uuuu PC + 1(2) uuuq quuu(3) uuuu uuuu 11uu uuuu ---u uuuu uuuu uqqq(1) -q-- ----(4) uuuu uquu(5) uuuu uuuu --uu uuuu -u-- ------- --uuuuu uu----- -uuu
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition Note 1: One or more bits in INTCON and PIR1 will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). 3: See Table 9-5 for RESET value for specific condition. 4: If wake-up was due to A/D completing then bit 6 = 1, all other interrupts generating a wake-up will cause bit 6 = u. 5: If wake-up was due to A/D completing then bit 3 = 0, all other interrupts generating a wake-up will cause bit 3 = u.
2002 Microchip Technology Inc.
Preliminary
DS41139B-page 57
PIC16C433
FIGURE 9-7: TIMEOUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
VDD MCLR INTERNAL POR TPWRT PWRT TIMEOUT
TOST
OST TIMEOUT
INTERNAL RESET
FIGURE 9-8:
TIMEOUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
VDD MCLR INTERNAL POR TPWRT PWRT TIMEOUT
TOST
OST TIMEOUT
INTERNAL RESET
FIGURE 9-9:
TIMEOUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD)
VDD MCLR INTERNAL POR TPWRT PWRT TIMEOUT
TOST
OST TIMEOUT
INTERNAL RESET
DS41139B-page 58
Preliminary
2002 Microchip Technology Inc.
PIC16C433
FIGURE 9-10: EXTERNAL POWER-ON RESET CIRCUIT (FOR SLOW VDD POWER-UP)
VDD D R R1 MCLR C PIC16C433
FIGURE 9-12: EXTERNAL BROWN-OUT PROTECTION CIRCUIT 1
VDD 33k 10k 4.3k VDD
MCLR PIC16C433
Note 1: Note 1: External Power-on Reset circuit is required only if VDD power-up slope is too slow. The diode D helps discharge the capacitor quickly when VDD powers down. R < 40 k is recommended to make sure that voltage drop across R does not violate the device's electrical specification. R1 = 100 to 1 k will limit any current flowing into MCLR from external capacitor C, in the event of MCLR/VPP pin breakdown due to Electrostatic Discharge (ESD), or Electrical Overstress (EOS). 2:
This circuit will activate RESET when VDD goes below (Vz + 0.7V), where Vz = Zener voltage. Resistors should be adjusted for the characteristics of the transistor.
2:
3:
FIGURE 9-13: EXTERNAL BROWN-OUT PROTECTION CIRCUIT 2
VDD R1
VDD Q1 MCLR
FIGURE 9-11: EXTERNAL BROWN-OUT PROTECTION CIRCUIT 3
VDD MCP809 VSS VDD RST MCLR PIC16C433 Bypass Capacitor VDD Note 1:
R2
4.3k
PIC16C433
This brown-out circuit is less expensive, albeit less accurate. Transistor Q1 turns off when VDD is below a certain level, such that: R1 = 0.7V VDD * R1 + R2
This brown-out protection circuit employs Microchip Technology's MCP809 microcontroller supervisor. The MCP8XX and MCP1XX families of supervisors provide push-pull and open collector outputs, with both high and low active RESET pins. There are 7 different trip point selections to accommodate 5V and 3V systems.
2: Resistors should be adjusted for the characteristics of the transistor.
2002 Microchip Technology Inc.
Preliminary
DS41139B-page 59
PIC16C433
9.5 Interrupts
There are four sources of interrupt: Interrupt Sources TMR0 Overflow Interrupt External Interrupt GP2/INT pin GPIO Port Change Interrupts (pins GP0, GP1, GP3) A/D Interrupt The Interrupt Control Register (INTCON) records individual interrupt requests in flag bits. It also has individual and global interrupt enable bits. Note: Individual interrupt flag bits are set, regardless of the status of their corresponding mask bit, or the GIE bit. The "return-from-interrupt" instruction, RETFIE, exits the interrupt routine, as well as sets the GIE bit, which re-enables interrupts. The GP2/INT, GPIO port change interrupt and the TMR0 overflow interrupt flags are contained in the INTCON register. The peripheral interrupt flag ADIF, is contained in the Special Function Register PIR1. The corresponding interrupt enable bit is contained in Special Function Register PIE1, and the peripheral interrupt enable bit is contained in Special Function Register INTCON. When an interrupt is responded to, the GIE bit is cleared to disable any further interrupt, the return address is pushed onto the stack and the PC is loaded with 0004h. Once in the Interrupt Service Routine, the source(s) of the interrupt can be determined by polling the interrupt flag bits. The interrupt flag bit(s) must be cleared in software before re-enabling interrupts to avoid repeated interrupts. For external interrupt events, such as GPIO change interrupt, the interrupt latency will be three or four instruction cycles. The exact latency depends on when the interrupt event occurs (Figure 9-15). The latency is the same for one or two cycle instructions. Individual interrupt flag bits are set, regardless of the status of their corresponding mask bit or the GIE bit.
A global interrupt enable bit, GIE (INTCON<7>), enables (if set) all unmasked interrupts, or disables (if cleared) all interrupts. When bit GIE is enabled and an interrupt's flag bit and mask bit are set, the interrupt will vector immediately. Individual interrupts can be disabled through their corresponding enable bits in various registers. Individual interrupt flag bits are set, regardless of the status of their corresponding mask bit or the GIE bit. The GIE bit is cleared on RESET.
FIGURE 9-14: INTERRUPT LOGIC
T0IF T0IE INTF INTE GPIF GPIE ADIF ADIE PEIE Interrupt to CPU Wake-up (If in SLEEP mode)
GIE
DS41139B-page 60
Preliminary
2002 Microchip Technology Inc.
PIC16C433
FIGURE 9-15: INT PIN INTERRUPT TIMING
Q1 OSC1 CLKOUT 3 4 INT pin INTF Flag (INTCON<1>) GIE bit (INTCON<7>) INSTRUCTION FLOW PC Instruction Fetched Instruction Executed PC Inst (PC) Inst (PC-1) PC+1 Inst (PC+1) Inst (PC) PC+1 -- Dummy Cycle 0004h Inst (0004h) Dummy Cycle 0005h Inst (0005h) Inst (0004h) 1 5 1 Interrupt Latency 2 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Note 1: INTF flag is sampled here (every Q1). 2: Interrupt latency = 3-4 TCY where TCY = instruction cycle time. Latency is the same whether Inst (PC) is a single cycle, or a 2-cycle instruction. 3: CLKOUT is available only in INTRC and EXTRC oscillator modes. 4: For minimum width of INT pulse, refer to AC specs. 5: INTF is enabled to be set any time during the Q4-Q1 cycles.
2002 Microchip Technology Inc.
Preliminary
DS41139B-page 61
PIC16C433
9.5.1 TMR0 INTERRUPT
9.6
Context Saving During Interrupts
An overflow (FFh 00h) in the TMR0 register will set flag bit T0IF (INTCON<2>). The interrupt can be enabled/disabled by setting/clearing enable bit T0IE (INTCON<5>) (see Section 7.0). The flag bit T0IF (INTCON<2>) will be set, regardless of the state of the enable bits. If used, this flag must be cleared in software. 9.5.2 INT INTERRUPT
During an interrupt, only the return PC value is saved on the stack. Typically, users may wish to save key registers during an interrupt (i.e., W register and STATUS register). This will have to be implemented in software. Example 9-1 shows the storing and restoring of the STATUS and W registers. The register, W_TEMP, must be defined in both banks and must be defined at the same offset from the bank base address (i.e., if W_TEMP is defined at 0x20 in bank 0, it must also be defined at 0xA0 in bank 1). Example 9.7 shows the saving and restoring of STATUS and W using RAM locations 0x70 - 0x7F. W_TEMP is defined at 0x70 and STATUS_TEMP is defined at 0x71. The example: a) b) c) d) e) f) Stores the W register. Stores the STATUS register in bank 0. Executes the ISR code. Restores the STATUS register (and bank select bit). Restores the W register. Returns from interrupt.
External interrupt on GP2/INT pin is edge triggered; either rising if bit INTEDG (OPTION<6>) is set, or falling, if the INTEDG bit is clear. When a valid edge appears on the GP2/INT pin, flag bit INTF (INTCON<1>) is set. This interrupt can be disabled by clearing enable bit INTE (INTCON<4>). Flag bit INTF must be cleared in software in the Interrupt Service Routine before re-enabling this interrupt. The INT interrupt can wake-up the processor from SLEEP, if bit INTE was set prior to going into SLEEP. The status of global interrupt enable bit GIE decides whether or not the processor branches to the interrupt vector following wakeup. See Section 9.8 for details on SLEEP mode. 9.5.3 GPIO INTCON CHANGE
An input change on GP3, GP1 or GP0 sets flag bit GPIF (INTCON<0>). The interrupt can be enabled/disabled by setting/clearing enable bit GPIE (INTCON<3>) (Section 5.1). This flag bit GPIF (INTCON<0>) will be set, regardless of the state of the enable bits. If used, this flag must be cleared in software.
EXAMPLE 9-1:
MOVWF SWAPF BCF MOVWF : :(ISR) : SWAPF MOVWF SWAPF SWAPF RETFIE
SAVING STATUS AND W REGISTERS USING GENERAL PURPOSE RAM (0x20 - 0x6F)
;Copy W to TEMP ;Swap status to ;Change to bank ;Save status to register, could be bank one or zero be saved into W zero, regardless of current bank bank zero STATUS_TEMP register
W_TEMP STATUS,W STATUS,RP0 STATUS_TEMP
STATUS_TEMP,W STATUS W_TEMP,F W_TEMP,W
;Swap STATUS_TEMP register into W ;(sets bank to original state) ;Move W into STATUS register ;Swap W_TEMP ;Swap W_TEMP into W ;Return from interrupt
DS41139B-page 62
Preliminary
2002 Microchip Technology Inc.
PIC16C433
EXAMPLE 9-2:
MOVWF MOVF MOVWF : :(ISR) : MOVF MOVWF SWAPF SWAPF RETFIE
Saving STATUS and W Registers using Shared RAM (0x70 - 0x7F)
;Copy W to TEMP register (bank independent) ;Move STATUS register into W ;Save contents of STATUS register
W_TEMP STATUS,W STATUS_TEMP
STATUS_TEMP,W STATUS W_TEMP,F W_TEMP,W
;Retrieve copy of STATUS register ;Restore pre-isr STATUS register contents ; ;Restore pre-isr W register contents ;Return from interrupt
9.7
Watchdog Timer (WDT)
The Watchdog Timer is a free running, on-chip RC oscillator which does not require any external components. This RC oscillator is separate from the RC oscillator of the OSC1/CLKIN pin. That means that the WDT will run, even if the clock on the OSC1/CLKIN and OSC2/CLKOUT pins of the device has been stopped, for example, by execution of a SLEEP instruction. During normal operation, a WDT timeout generates a device RESET (Watchdog Timer Reset). If the device is in SLEEP mode, a WDT timeout causes the device to wake-up and continue with normal operation (Watchdog Timer Wakeup). The WDT can be permanently disabled by clearing configuration bit WDTE (Section 9.1). 9.7.1 WDT PERIOD
The WDT has a nominal timeout period of 18 ms (with no prescaler). The timeout periods vary with temperature, VDD and process variations from part to part (see DC specs). If longer timeout periods are desired, a prescaler with a division ratio of up to 1:128 can be assigned to the WDT under software control, by writing to the OPTION register. Thus, timeout periods up to 2.3 seconds can be realized. The CLRWDT and SLEEP instructions clear the WDT and the postscaler, if assigned to the WDT, and prevent it from timing out early and generating a premature device RESET condition. The TO bit in the STATUS register will be cleared upon a Watchdog Timer timeout. 9.7.2 WDT PROGRAMMING CONSIDERATIONS
It should also be taken into account that under worst case conditions (VDD = Min., Temperature = Max., and Max. WDT prescaler), it may take several seconds before a WDT timeout occurs. Note: When the prescaler is assigned to the WDT, always execute a CLRWDT instruction before changing the prescale value, otherwise a WDT Reset may occur.
See Example 7-1 and Example 7-2 for changing prescaler between WDT and Timer0.
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FIGURE 9-16: WATCHDOG TIMER BLOCK DIAGRAM
From TMR0 Clock Source (Figure 7-5) 0 WDT Timer 1 M U X Postscaler 8 8 - to - 1 MUX WDT Enable Bit PSA To TMR0 (Figure 7-5) 0 MUX 1 PSA PS<2:0>
Note: PSA and PS<2:0> are bits in the OPTION register.
WDT Timeout
TABLE 9-8:
Address 2007h 81h
SUMMARY OF WATCHDOG TIMER REGISTERS
Name Config. bits(1) OPTION Bit 7 MCLRE GPPU Bit 6 CP1 INTEDG Bit 5 CP0 T0CS Bit 4 PWRTE T0SE Bit 3 WDTE PSA Bit 2 FOSC2 PS2 Bit 1 FOSC1 PS1 Bit 0 FOSC0 PS0
Legend: Shaded cells are not used by the Watchdog Timer. Note 1: See Register 9-1 for operation of these bits. Not all CP0 and CP1 bits are shown.
9.8
Power-down Mode (SLEEP)
Power-down mode is entered by executing a SLEEP instruction. If enabled, the Watchdog Timer will be cleared but keeps running, the PD bit (STATUS<3>) is cleared, the TO (STATUS<4>) bit is set, and the oscillator driver is turned off. The I/O ports maintain the status they had before the SLEEP instruction was executed (driving high, low or hi-impedance). For lowest current consumption in this mode, place all I/O pins at either VDD or VSS, ensure no external circuitry is drawing current from the I/O pin, power-down the A/D, and disable external clocks. Pull all I/O pins that are hi-impedance inputs, high or low externally, to avoid switching currents caused by floating inputs. The T0CKI input, if enabled, should also be at VDD or VSS, for lowest current consumption. The contribution from on-chip pull-ups on GPIO should be considered. The MCLR pin, if enabled, must be at a logic high level (VIHMC). 9.8.1 WAKE-UP FROM SLEEP
1. 2. 3. 4.
External RESET input on MCLR pin. Watchdog Timer Wake-up (if WDT was enabled). GP2/INT interrupt, interrupt GPIO port change or some peripheral interrupts. LIN bus activity (connect BACT to GP2/T0CKI/ AN2/INT pin).
External MCLR Reset will cause a device RESET. All other events are considered a continuation of program execution and cause a wake-up. The TO and PD bits in the STATUS register can be used to determine the cause of device RESET. The PD bit, which is set on power-up, is cleared when SLEEP is invoked. The TO bit is cleared if a WDT timeout occurred (and caused wake-up). The following peripheral interrupt can wake the device from SLEEP: 1. A/D conversion (when A/D clock source is RC). Other peripherals cannot generate interrupts since during SLEEP, no on-chip Q clocks are present. When the SLEEP instruction is being executed, the next instruction (PC + 1) is pre-fetched. For the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be set (enabled). Wake-up is
The device can wake-up from SLEEP through one of the following events:
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regardless of the state of the GIE bit. If the GIE bit is clear (disabled), the device continues execution at the instruction after the SLEEP instruction. If the GIE bit is set (enabled), the device executes the instruction after the SLEEP instruction and then branches to the interrupt address (0004h). In cases where the execution of the instruction following SLEEP is not desirable, the user should have a NOP after the SLEEP instruction. 9.8.2 WAKE-UP USING INTERRUPTS instruction will be completely executed before the wake-up. Therefore, the WDT and WDT postscaler will be cleared, the TO bit will be set and the PD bit will be cleared. Even if the flag bits were checked before executing a SLEEP instruction, it may be possible for flag bits to become set before the SLEEP instruction completes. To determine whether a SLEEP instruction executed, test the PD bit. If the PD bit is set, the SLEEP instruction was executed as a NOP. To ensure that the WDT is cleared, a CLRWDT instruction should be executed before a SLEEP instruction. 9.8.3 WAKE-UP FROM SLEEP UPON BUS ACTIVITY
When global interrupts are disabled (GIE cleared) and any interrupt source has both its interrupt enable bit and interrupt flag bit set, one of the following will occur: * If the interrupt occurs before the execution of a SLEEP instruction, the SLEEP instruction will complete as a NOP. Therefore, the WDT and WDT postscaler will not be cleared, the TO bit will not be set and PD bits will not be cleared. * If the interrupt occurs during or after the execution of a SLEEP instruction, the device will immediately wake-up from SLEEP. The SLEEP
The can be woken up upon bus activity on the LIN bus. This is done by connecting the BACT pin with either GP0, GP1 or GP2. The pin which will be connected to the BACT pin has to be configured to wake the microcontroller up from SLEEP.
FIGURE 9-17: WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 OSC1 CLKOUT(4) GPIO pin GPIF Flag (INTCON<0>) GIE bit (INTCON<7>) INSTRUCTION FLOW PC Instruction Fetched Instruction Executed Note 1: 2: 3: 4: PC Inst(PC)=SLEEP Inst(PC - 1) PC+1 Inst(PC + 1) SLEEP PC+2 PC+2 Inst(PC + 2) Inst(PC + 1) Dummy cycle PC + 2 0004h Inst(0004h) Dummy cycle 0005h Inst(0005h) Inst(0004h) Processor in SLEEP Interrupt Latency (Note 3) TOST(2) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
XT, HS or LP Oscillator mode assumed. TOST = 1024TOSC (drawing not to scale). This delay will not be there for INTRC and EXTRC osc mode. GIE = '1' assumed. In this case, after wakeup, the processor jumps to the interrupt routine. If GIE = '0', execution will continue in-line. CLKOUT is not available in XT, HS or LP osc modes, but shown here for timing reference.
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9.9 Program Verification/Code Protection
If the code protection bit(s) have not been programmed, the on-chip program memory can be read out for verification purposes. Note: Microchip does not recommend code protecting windowed devices.
FIGURE 9-18: TYPICAL IN-CIRCUIT SERIAL PROGRAMMING CONNECTION
To Normal Connections
External Connector Signals +5V
PIC16C433
VDD VSS MCLR/VPP GP1 GP0
9.10
ID Locations
0V VPP CLK Data I/O
Four memory locations (2000h - 2003h) are designated as ID locations, where the user can store checksum or other code identification numbers. These locations are not accessible during normal execution, but are readable and writable during Program/Verify. It is recommended that only the 4 Least Significant bits of the ID location are used.
9.11
In-Circuit Serial Programming
To Normal Connections
VDD
PIC16C433 microcontrollers can be serially programmed, while in the end application circuit. This is simply done with two lines for clock and data, and three other lines for power, ground and the programming voltage. This allows customers to manufacture boards with unprogrammed devices, and then program the microcontroller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed. The device is placed into a Program/Verify mode by holding the GP1 and GP0 pins low, while raising the MCLR (VPP) pin from VIL to VIHH (see programming specification). GP1 (clock) becomes the programming clock and GP0 (data) becomes the programming data. Both GP0 and GP1 are Schmitt Trigger inputs in this mode. After RESET, and if the device is placed into Programming/Verify mode, the program counter (PC) is at location 00h. A 6-bit command is then supplied to the device. Depending on the command, 14 bits of program data are then supplied to or from the device, depending if the command was a load or a read. For complete details of serial programming, please refer to the PIC16C433 Programming Specifications.
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10.0 INSTRUCTION SET SUMMARY
Each PIC16C433 instruction is a 14-bit word divided into an OPCODE which specifies the instruction type and one or more operands which further specify the operation of the instruction. The PIC16C433 instruction set summary in Table 10-2 lists byte-oriented, bit-oriented, and literal and control operations. Table 10-1 shows the opcode field descriptions. For byte-oriented instructions, 'f' represents a file register designator and 'd' represents a destination designator. The file register designator specifies which file register is to be used by the instruction. The destination designator specifies where the result of the operation is to be placed. If 'd' is zero, the result is placed in the W register. If 'd' is one, the result is placed in the file register specified in the instruction. For bit-oriented instructions, 'b' represents a bit field designator which selects the number of the bit affected by the operation, while 'f' represents the address of the file in which the bit is located. For literal and control operations, 'k' represents an eight or eleven bit constant or literal value. * Byte-oriented operations * Bit-oriented operations * Literal and control operations All instructions are executed within one single instruction cycle, unless a conditional test is true or the program counter is changed as a result of an instruction. In this case, the execution takes two instruction cycles with the second cycle executed as a NOP. One instruction cycle consists of four oscillator periods. Thus, for an oscillator frequency of 4 MHz, the normal instruction execution time is 1 s. If a conditional test is true or the program counter is changed as a result of an instruction, the instruction execution time is 2 s. Table 10-2 lists the instructions recognized by the MPASMTM assembler. Figure 10-1 shows the three general formats that the instructions can have. Note: To maintain upward compatibility with future PIC16C433 products, do not use the OPTION and TRIS instructions.
All examples use the following format to represent a hexadecimal number: 0xhh where h signifies a hexadecimal digit.
TABLE 10-1:
Field f W b k x
OPCODE FIELD DESCRIPTIONS
Description
Register file address (0x00 to 0x7F) Working register (accumulator) Bit address within an 8-bit file register Literal field, constant data or label Don't care location (= 0 or 1) The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools.
FIGURE 10-1: GENERAL FORMAT FOR INSTRUCTIONS
Byte-oriented file register operations 13 876 OPCODE d f (FILE #) d = 0 for destination W d = 1 for destination f f = 7-bit file register address Bit-oriented file register operations 13 10 9 76 OPCODE b (BIT #) f (FILE #) b = 3-bit bit address f = 7-bit file register address Literal and control operations General 13 87 OPCODE k = 8-bit immediate value CALL and GOTO instructions only 13 11 OPCODE 10 k (literal) 0 0 0
Destination select; d = 0: store result in W, d = 1: store result in file register f. Default is d = 1. label Label name d TOS PC GIE WDT TO PD Top-of-Stack Program Counter Global Interrupt Enable bit Watchdog Timer/Counter Timeout bit
PCLATH Program Counter High Latch
0 k (literal)
Power-down bit dest Destination either the W register or the specified register file location [] Options Contents Assigned to Register bit field In the set of User defined term (font is courier)
() <> italics
k = 11-bit immediate value
The instruction set is highly orthogonal and is grouped into three basic categories:
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10.1 Special Function Registers as Source/Destination
10.1.3 PCL AS SOURCE OR DESTINATION The PIC16C433's orthogonal instruction set allows read and write of all file registers, including special function registers. There are some special situations specified in the following sections the user should be aware of. 10.1.1 STATUS AS DESTINATION Read, write or read-modify-write on PCL may have the following results: Read PC: Write PCL: Read-Modify-Write: If an instruction writes to STATUS, the Z, C and DC bits may be set or cleared as a result of the instruction and overwrite the original data bits written. For example, executing CLRF STATUS will clear register STATUS, and then set the Z bit leaving 0000 0100b in the register. 10.1.2 TRIS AS DESTINATION PCL dest PCLATH PCH; 8-bit destination value PCL PCL ALU operand PCLATH PCH; 8-bit result PCL
Where PCH = program counter high byte (not an addressable register), PCLATH = Program counter high holding latch, dest = destination, WREG or f. 10.1.4 BIT MANIPULATION
Bit 3 of the TRIS register always reads as a '1' since GP3 is an input only pin. This fact can affect some read-modify-write operations on the TRIS register.
All bit manipulation instructions are done by first reading the entire register, operating on the selected bit and writing the result back (read-modify-write). The user should keep this in mind when operating on special function registers, such as ports.
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TABLE 10-2:
Mnemonic, Operands
INSTRUCTION SET SUMMARY
14-Bit Opcode Description Cycles MSb LSb Status Affected Notes
BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF f, d f, d f f, d f, d f, d f, d f, d f, d f, d f f, d f, d f, d f, d f, d Add W and f AND W with f Clear f Clear W Complement f Decrement f Decrement f, Skip if 0 Increment f Increment f, Skip if 0 Inclusive OR W with f Move f Move W to f No Operation Rotate Left f through Carry Rotate Right f through Carry Subtract W from f Swap nibbles in f Exclusive OR W with f 1 1 1 1 1 1 1(2) 1 1(2) 1 1 1 1 1 1 1 1 1 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0111 0101 0001 0001 1001 0011 1011 1010 1111 0100 1000 0000 0000 1101 1100 0010 1110 0110 dfff dfff lfff 0000 dfff dfff dfff dfff dfff dfff dfff lfff 0xx0 dfff dfff dfff dfff dfff ffff ffff ffff 0011 ffff ffff ffff ffff ffff ffff ffff ffff 0000 ffff ffff ffff ffff ffff C,DC,Z Z Z Z Z Z Z Z Z 1,2 1,2 2 1,2 1,2 1,2,3 1,2 1,2,3 1,2 1,2
C C C,DC,Z Z
1,2 1,2 1,2 1,2 1,2
BIT-ORIENTED FILE REGISTER OPERATIONS BCF BSF BTFSC BTFSS f, b f, b f, b f, b Bit Clear f Bit Set f Bit Test f, Skip if Clear Bit Test f, Skip if Set 1 1 1 (2) 1 (2) 01 01 01 01 00bb 01bb 10bb 11bb bfff bfff bfff bfff ffff ffff ffff ffff 1,2 1,2 3 3
LITERAL AND CONTROL OPERATIONS ADDLW ANDLW CALL CLRWDT GOTO IORLW MOVLW RETFIE RETLW RETURN SLEEP SUBLW XORLW Note 1: k k k k k k k k k Add literal and W AND literal with W Call subroutine Clear Watchdog Timer Go to address Inclusive OR literal with W Move literal to W Return from interrupt Return with literal in W Return from Subroutine Go into Standby mode Subtract W from literal Exclusive OR literal with W 1 1 2 1 2 1 1 2 2 2 1 1 1 11 11 10 00 10 11 11 00 11 00 00 11 11 111x 1001 0kkk 0000 1kkk 1000 00xx 0000 01xx 0000 0000 110x 1010 kkkk kkkk kkkk 0110 kkkk kkkk kkkk 0000 kkkk 0000 0110 kkkk kkkk kkkk kkkk kkkk 0100 kkkk kkkk kkkk 1001 kkkk 1000 0011 kkkk kkkk C,DC,Z Z TO,PD Z
TO,PD C,DC,Z Z
2: 3:
When an I/O register is modified as a function of itself ( i.e., MOVF PORTB, 1), the value used will be that value present on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven low by an external device, the data will be written back with a '0'. If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned to the Timer0 Module. If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP.
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10.2
ADDLW Syntax: Operands: Operation: Status Affected: Encoding: Description:
Instruction Descriptions
Add Literal and W [ label ] ADDLW 0 k 255 (W) + k (W) C, DC, Z
11 111x kkkk kkkk
ANDLW k Syntax: Operands: Operation: Status Affected: Encoding: Description:
And Literal with W [ label ] ANDLW 0 k 255 (W) .AND. (k) (W) Z
11 1001 kkkk kkkk
k
The contents of the W register are added to the eight bit literal 'k' and the result is placed in the W register. 1 1
ADDLW 0x15 W W = = 0x10 0x25
The contents of W register are AND'ed with the eight bit literal 'k'. The result is placed in the W register. 1 1
ANDLW W W 0x5F = = 0xA3 0x03
Words: Cycles: Example
Words: Cycles: Example
Before Instruction After Instruction
Before Instruction After Instruction
ADDWF Syntax: Operands: Operation: Status Affected: Encoding: Description:
Add W and f [ label ] ADDWF 0 f 127 d [0,1] (W) + (f) (dest) C, DC, Z
00 0111 dfff ffff
ANDWF f,d Syntax: Operands: Operation: Status Affected: Encoding: Description:
AND W with f [ label ] ANDWF 0 f 127 d [0,1] (W) .AND. (f) (dest) Z
00 0101 dfff ffff
f,d
Add the contents of the W register with register 'f'. If 'd' is 0, the result is stored in the W register. If 'd' is 1, the result is stored back in register 'f'. 1 1
ADDWF FSR, 0 W= FSR = 0x17 0xC2 0xD9 0xC2
AND the W register with register 'f'. If 'd' is 0, the result is stored in the W register. If 'd' is 1, the result is stored back in register 'f'. 1 1
ANDWF FSR, 1 W= FSR = 0x17 0xC2 0x17 0x02
Words: Cycles: Example
Words: Cycles: Example
Before Instruction After Instruction
W= FSR =
Before Instruction After Instruction
W= FSR =
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BCF Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Example 1 1
BCF FLAG_REG, 7 FLAG_REG = 0xC7
Bit Clear f [ label ] BCF 0 f 127 0b7 0 (f) None
01 00bb bfff ffff
BTFSC f,b Syntax: Operands: Operation: Status Affected: Encoding: Description:
Bit Test, Skip if Clear [ label ] BTFSC f,b 0 f 127 0b7 skip if (f) = 0 None
01 10bb bfff ffff
Bit 'b' in register 'f' is cleared.
Before Instruction After Instruction
FLAG_REG = 0x47
If bit 'b' in register 'f' is '0', then the next instruction is skipped. If bit 'b' is '0', then the next instruction fetched during the current instruction execution is discarded, and a NOP is executed instead, making this a 2 cycle instruction. 1 1(2)
HERE FALSE TRUE BTFSC GOTO * * * PC = FLAG,1 PROCESS_CODE
Words: Cycles: Example
Before Instruction
address HERE
After Instruction
if FLAG<1> = 0, PC = address TRUE if FLAG<1>=1, PC = address FALSE
BSF Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Example
Bit Set f [ label ] BSF 0 f 127 0b7 1 (f) None
01 01bb bfff ffff
f,b
Bit 'b' in register 'f' is set. 1 1
BSF FLAG_REG, 7
Before Instruction
FLAG_REG = 0x0A
After Instruction
FLAG_REG = 0x8A
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BTFSS Syntax: Operands: Operation: Status Affected: Encoding: Description: Bit Test f, Skip if Set [ label ] BTFSS f,b 0 f 127 0b<7 skip if (f) = 1 None
01 11bb bfff ffff
CLRF Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Example
Clear f [ label ] CLRF 0 f 127 00h (f) 1Z Z
00 0001 1fff ffff
f
If bit 'b' in register 'f' is '1', then the next instruction is skipped. If bit 'b' is '1', then the next instruction fetched during the current instruction execution is discarded and a NOP is executed instead, making this a 2-cycle instruction. 1 1(2)
HERE FALSE TRUE BTFSS GOTO * * * PC = FLAG,1 PROCESS_CODE
The contents of register 'f' are cleared and the Z bit is set. 1 1
CLRF FLAG_REG FLAG_REG = = = 0x5A 0x00 1
Before Instruction After Instruction
FLAG_REG Z
Words: Cycles: Example
Before Instruction
address HERE
After Instruction
if FLAG<1> = 0, PC = address FALSE if FLAG<1> = 1, PC = address TRUE
CALL Syntax: Operands: Operation:
Call Subroutine [ label ] CALL k 0 k 2047 (PC)+ 1 TOS, k PC<10:0>, (PCLATH<4:3>) PC<12:11> None
10 0kkk kkkk kkkk
CLRW Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Example
Clear W [ label ] CLRW None 00h (W) 1Z Z
00 0001 0000 0011
Status Affected: Encoding: Description:
Call Subroutine. First, return address (PC+1) is pushed onto the stack. The eleven bit immediate address is loaded into PC bits <10:0>. The upper bits of the PC are loaded from PCLATH. CALL is a two-cycle instruction. 1 2
HERE CALL THERE
W register is cleared. Zero bit (Z) is set. 1 1
CLRW
Before Instruction
W W Z = = = 0x5A 0x00 1
Words: Cycles: Example
After Instruction
Before Instruction
PC = Address HERE
After Instruction
PC = Address THERE TOS = Address HERE+1
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CLRWDT Syntax: Operands: Operation: Clear Watchdog Timer [ label ] CLRWDT None 00h WDT 0 WDT prescaler, 1 TO 1 PD TO, PD
00 0000 0110 0100
DECF Syntax: Operands: Operation: Status Affected: Encoding: Description:
Decrement f [ label ] DECF f,d 0 f 127 d [0,1] (f) - 1 (dest) Z
00 0011 dfff ffff
Status Affected: Encoding: Description:
CLRWDT instruction resets the Watchdog Timer. It also resets the prescaler of the WDT. Status bits TO and PD are set. 1 1
CLRWDT
Decrement register 'f'. If 'd' is 0, the result is stored in the W register. If 'd' is 1, the result is stored back in register 'f'. 1 1
DECF CNT, 1 CNT Z = = = = 0x01 0 0x00 1
Words: Cycles: Example
Words: Cycles: Example
Before Instruction After Instruction
CNT Z
Before Instruction
WDT counter = ? 0x00 0 1 1
After Instruction
WDT counter = WDT prescaler= TO = PD =
DECFSZ Syntax: Operands:
Decrement f, Skip if 0 [ label ] DECFSZ f,d 0 f 127 d [0,1] (f) - 1 (dest);
00 1011
COMF Syntax: Operands: Operation: Status Affected: Encoding: Description:
Complement f [ label ] COMF 0 f 127 d [0,1] (f) (dest) Z
00 1001 dfff ffff
f,d
Operation: Encoding: Description:
skip if result = 0
dfff ffff
Status Affected: None The contents of register 'f' are decremented. If 'd' is 0, the result is placed in the W register. If 'd' is 1, the result is placed back in register 'f'. If the result is 0, the next instruction, which is already fetched, is discarded. A NOP is executed instead making it a two-cycle instruction. 1 1(2)
HERE DECFSZ GOTO CONTINUE * * * CNT, 1 LOOP
The contents of register 'f' are complemented. If 'd' is 0, the result is stored in W. If 'd' is 1, the result is stored back in register 'f'. 1 1
COMF REG1,0 REG1 = = = 0x13 0x13 0xEC
Words: Cycles: Example
Words: Cycles: Example
Before Instruction After Instruction
REG1 W
Before Instruction
PC =
address HERE CNT - 1 0, address CONTINUE 0, address HERE+1
After Instruction
CNT if CNT PC if CNT PC = = = 1/4 =
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GOTO Syntax: Operands: Operation: Status Affected: Encoding: Description: Unconditional Branch [ label ] GOTO k 0 k 2047 k PC<10:0> PCLATH<4:3> PC<12:11> None
10 1kkk kkkk kkkk
INCF Syntax: Operands: Operation: Status Affected: Encoding: Description:
Increment f [ label ] INCF f,d 0 f 127 d [0,1] (f) + 1 (dest) Z
00 1010 dfff ffff
GOTO is an unconditional branch. The eleven-bit immediate value is loaded into PC bits <10:0>. The upper bits of PC are loaded from PCLATH<4:3>. GOTO is a twocycle instruction. 1 2
GOTO THERE
The contents of register 'f' are incremented. If 'd' is 0, the result is placed in the W register. If 'd' is 1, the result is placed back in register 'f'. 1 1
INCF CNT, 1 CNT Z = = = = 0xFF 0 0x00 1
Words: Cycles: Example
Words: Cycles: Example
Before Instruction
Address THERE
After Instruction
PC =
After Instruction
CNT Z
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INCFSZ Syntax: Operands: Operation: Status Affected: Encoding: Description: Increment f, Skip if 0 [ label ] INCFSZ f,d 0 f 127 d [0,1] (f) + 1 (dest), skip if result = 0 None
00 1111 dfff ffff
IORWF Syntax: Operands: Operation: Status Affected: Encoding: Description:
Inclusive OR W with f [ label ] IORWF f,d 0 f 127 d [0,1] (W) .OR. (f) (dest) Z
00 0100 dfff ffff
The contents of register 'f' are incremented. If 'd' is 0, the result is placed in the W register. If 'd' is 1, the result is placed back in register 'f'. If the result is 0, the next instruction, which is already fetched, is discarded. A NOP is executed instead making it a two-cycle instruction. 1 1(2)
HERE INCFSZ GOTO CONTINUE * * * CNT, LOOP 1
Inclusive OR the W register with register 'f'. If 'd' is 0, the result is placed in the W register. If 'd' is 1, the result is placed back in register 'f'. 1 1
IORWF RESULT, 0 RESULT = W = 0x13 0x91 0x13 0x93 1
Words: Cycles: Example
Before Instruction After Instruction
RESULT = W = Z =
Words: Cycles: Example
Before Instruction
PC = address HERE CNT + 1 0, address CONTINUE 0, address HERE +1
MOVLW Syntax: Operands: Operation: Status Affected: Encoding: Description:
Move Literal to W [ label ] k (W) None
11 00xx kkkk kkkk
After Instruction
CNT = if CNT= PC = if CNT PC =
MOVLW k
0 k 255
IORLW Syntax: Operands: Operation: Status Affected: Encoding: Description:
Inclusive OR Literal with W [ label ] IORLW k 0 k 255 (W) .OR. k (W) Z
11 1000 kkkk kkkk
The eight-bit literal 'k' is loaded into W register. The don't cares will assemble as 0's. 1 1
MOVLW W 0x5A = 0x5A
Words: Cycles: Example
After Instruction
The contents of the W register are OR'ed with the eight bit literal 'k'. The result is placed in the W register. 1 1
IORLW W W Z 0x35 = = = 0x9A 0xBF 1
Words: Cycles: Example
Before Instruction After Instruction
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PIC16C433
MOVF Syntax: Operands: Operation: Status Affected: Encoding: Description: Move f [ label ] MOVF f,d 0 f 127 d [0,1] (f) (dest) Z
00 1000 dfff ffff
NOP Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Example
No Operation [ label ] None No operation None
00 0000 0xx0 0000
NOP
No operation. 1 1
NOP
The contents of register f are moved to a destination dependant upon the status of d. If d = 0, destination is W register. If d = 1, the destination is file register f itself. d = 1 is useful to test a file register since status flag Z is affected. 1 1
MOVF FSR, 0 W = value in FSR register Z =1
Words: Cycles: Example
After Instruction
MOVWF Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Example
Move W to f [ label ] (W) (f) None
00 0000 1fff ffff
OPTION Syntax: f Operands: Operation: Status Affected: Encoding: Description:
Load Option Register [ label ] None (W) OPTION None
00 0000 0110 0010
OPTION
MOVWF
0 f 127
Move data from W register to register 'f'. 1 1
MOVWF OPTION
The contents of the W register are loaded in the OPTION register. This instruction is supported for code compatibility with PIC16C5X products. Since OPTION is a readable/writable register, the user can directly address it. 1 1
To maintain upward compatibility with future PIC16C433 products, do not use this instruction.
Before Instruction
OPTION = W = 0xFF 0x4F 0x4F 0x4F
Words: Cycles: Example
After Instruction
OPTION = W =
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PIC16C433
RETFIE Syntax: Operands: Operation: Status Affected: Encoding: Description: Return from Interrupt [ label ] None TOS PC, 1 GIE None
00 0000 0000 1001
RETURN Syntax: Operands: Operation: Status Affected: Encoding: Description:
Return from Subroutine [ label ] None TOS PC None
00 0000 0000 1000
RETFIE
RETURN
Return from Interrupt. Stack is POPed and Top-of-Stack (TOS) is loaded in the PC. Interrupts are enabled by setting Global Interrupt Enable bit, GIE (INTCON<7>). This is a two-cycle instruction. 1 2
RETFIE
Return from subroutine. The stack is POPed and the top of the stack (TOS) is loaded into the program counter. This is a two-cycle instruction. 1 2
RETURN
Words: Cycles: Example
Words: Cycles: Example
After Interrupt
PC = TOS
After Interrupt
PC = GIE = TOS 1
RETLW Syntax: Operands: Operation:
Return with Literal in W [ label ] RETLW k 0 k 255 k (W); TOS PC
11 01xx kkkk kkkk
Status Affected: None Encoding: Description: The W register is loaded with the eight-bit literal 'k'. The program counter is loaded from the top of the stack (the return address). This is a two-cycle instruction. 1 2
CALL TABLE;W contains table ;offset value * ;W now has table value
Words: Cycles: Example TABLE
* *
ADDWF PC RETLW k1 RETLW k2 ;W = offset ;Begin table ;
* * *
RETLW kn W W ; End of table = = 0x07 value of k8
Before Instruction After Instruction
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PIC16C433
RLF Syntax: Operands: Operation: Status Affected: Encoding: Description: Rotate Left f through Carry [ label ] RLF 0 f 127 d [0,1] See description below C
00 1101 dfff ffff
SLEEP Syntax: Operands: Operation: [ label ] SLEEP None 00h WDT, 0 WDT prescaler, 1 TO, 0 PD TO, PD
00 0000 0110 0011
f,d
The contents of register 'f' are rotated one bit to the left through the Carry Flag. If 'd' is 0, the result is placed in the W register. If 'd' is 1, the result is stored back in register 'f'.
C Register f
Status Affected: Encoding: Description:
The power-down status bit, PD is cleared. Timeout status bit, TO is set. Watchdog Timer and its prescaler are cleared. The processor is put into SLEEP mode with the oscillator stopped. 1 1 SLEEP
Words: Cycles: Example
1 1
RLF REG1,0 REG1 C = = = = = 1110 0110 0 1110 0110 1100 1100 1
Words: Cycles: Example:
Before Instruction After Instruction
REG1 W C
RRF Syntax: Operands: Operation: Status Affected: Encoding: Description:
Rotate Right f through Carry [ label ] RRF f,d 0 f 127 d [0,1] See description below C
00 1100 dfff ffff
The contents of register 'f' are rotated one bit to the right through the Carry Flag. If 'd' is 0, the result is placed in the W register. If 'd' is 1, the result is placed back in register 'f'.
C Register f
Words: Cycles: Example
1 1
RRF REG1 C REG1,0 = = = = = 1110 0110 0 1110 0110 0111 0011 0
Before Instruction After Instruction
REG1 W C
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PIC16C433
SUBLW Syntax: Operands: Operation: Status Affected: Encoding: Description: Subtract W from Literal [ label ] SUBLW k 0 k 255 k - (W) (W) C, DC, Z 11 110x kkkk kkkk Operation: Status Affected: Encoding: Description: SUBWF Syntax: Operands: Subtract W from f [ label ] SUBWF f,d 0 f 127 d [0,1] (f) - (W) (dest) C, DC, Z 00 0010 dfff ffff
The W register is subtracted (2's complement method) from the eight bit literal 'k'. The result is placed in the W register. 1 1 SUBLW 0x02
W C = = 1 ?
Words: Cycles: Example 1:
Subtract (2's complement method) W register from register 'f'. If 'd' is 0, the result is stored in the W register. If 'd' is 1, the result is stored back in register 'f'. 1 1 SUBWF
REG1 W C
Words: Cycles: Example 1:
Before Instruction
REG1,1
= = = 3 2 ?
Before Instruction
After Instruction
W C = = 1 1; result is positive
Example 2:
Before Instruction
W C = = 2 ?
After Instruction
REG1 W C = = = 1 2 1; result is positive
After Instruction
W C = = 0 1; result is zero
Example 2:
Before Instruction
REG1 W C = = = 2 2 ?
Example 3:
Before Instruction
W C = = 3 ?
After Instruction
REG1 W C = = = 0 2 1; result is zero
After Instruction
W C = = 0xFF 0; result is negative
Example 3:
Before Instruction
REG1 W C = = = 1 2 ?
After Instruction
REG1 W C = = = 0xFF 2 0; result is negative
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Preliminary
DS41139B-page 79
PIC16C433
SWAPF Syntax: Operands: Operation: Status Affected: Encoding: Description: Swap Nibbles in f [ label ] SWAPF f,d 0 f 127 d [0,1] (f<3:0>) (dest<7:4>), (f<7:4>) (dest<3:0>) None
00
XORLW Syntax: Operands: Operation: Status Affected: Encoding: ffff Description:
Exclusive OR Literal with W [ label ] XORLW k 0 k 255 (W) .XOR. k (W) Z 11 1010 kkkk kkkk The contents of the W register are XOR'ed with the eight bit literal 'k'. The result is placed in the W register. 1 1
XORLW 0xAF
1110
dfff
The upper and lower nibbles of register 'f' are exchanged. If 'd' is 0, the result is placed in W register. If 'd' is 1, the result is placed in register 'f'. 1 1
SWAPF REG, 0
Words: Cycles: Example:
Words: Cycles: Example
Before Instruction
W = 0xB5
Before Instruction
REG1 = 0xA5
After Instruction
W = 0x1A
After Instruction
REG1 W = = 0xA5 0x5A
TRIS Syntax: Operands: Operation: Status Affected: Encoding: Description:
Load TRIS Register [ label ] TRIS 5f7 (W) TRIS register f; None
00
XORWF Syntax: Operands: Operation:
Exclusive OR W with f [ label ] XORWF 0 f 127 d [0,1] (W) .XOR. (f) (dest) Z
00 0110 dfff ffff
f
f,d
0000
0110
0fff
Status Affected: Encoding: Description:
The instruction is supported for code compatibility with the PIC16C5X products. Since TRIS registers are readable and writable, the user can directly address them. 1 1
To maintain upward compatibility with future PIC16C433 products, do not use this instruction.
Exclusive OR the contents of the W register with register 'f'. If 'd' is 0, the result is stored in the W register. If 'd' is 1, the result is stored back in register 'f'. 1 1 XORWF
REG 1
Words: Cycles: Example
Words: Cycles: Example
Before Instruction
REG W = = 0xAF 0xB5
After Instruction
REG W = = 0x1A 0xB5
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Preliminary
2002 Microchip Technology Inc.
PIC16C433
11.0 DEVELOPMENT SUPPORT
11.1
The PICmicro(R) microcontrollers are supported with a full range of hardware and software development tools: * Integrated Development Environment - MPLAB(R) IDE Software * Assemblers/Compilers/Linkers - MPASMTM Assembler - MPLAB C17 and MPLAB C18 C Compilers - MPLINKTM Object Linker/ MPLIBTM Object Librarian - MPLAB C30 C Compiler - MPLAB ASM30 Assembler/Linker/Library * Simulators - MPLAB SIM Software Simulator - MPLAB dsPIC30 Software Simulator * Emulators - MPLAB ICE 2000 In-Circuit Emulator - MPLAB ICE 4000 In-Circuit Emulator * In-Circuit Debugger - MPLAB ICD 2 * Device Programmers - PRO MATE(R) II Universal Device Programmer - PICSTART(R) Plus Development Programmer * Low Cost Demonstration Boards - PICDEMTM 1 Demonstration Board - PICDEM.netTM Demonstration Board - PICDEM 2 Plus Demonstration Board - PICDEM 3 Demonstration Board - PICDEM 17 Demonstration Board - PICDEM 18R Demonstration Board - PICDEM LIN Demonstration Board - PICDEM USB Demonstration Board * Evaluation Kits - KEELOQ(R) - PICDEM MSC - microID(R) - CAN - PowerSmart(R) - Analog
MPLAB Integrated Development Environment Software
The MPLAB IDE software brings an ease of software development previously unseen in the 8/16-bit microcontroller market. The MPLAB IDE is a Windows(R) based application that contains: * An interface to debugging tools - simulator - programmer (sold separately) - emulator (sold separately) - in-circuit debugger (sold separately) * A full-featured editor with color coded context * A multiple project manager * Customizable data windows with direct edit of contents * High level source code debugging * Mouse over variable inspection * Extensive on-line help The MPLAB IDE allows you to: * Edit your source files (either assembly or C) * One touch assemble (or compile) and download to PICmicro emulator and simulator tools (automatically updates all project information) * Debug using: - source files (assembly or C) - absolute listing file (mixed assembly and C) - machine code MPLAB IDE supports multiple debugging tools in a single development paradigm, from the cost effective simulators, through low cost in-circuit debuggers, to full-featured emulators. This eliminates the learning curve when upgrading to tools with increasing flexibility and power.
11.2
MPASM Assembler
The MPASM assembler is a full-featured, universal macro assembler for all PICmicro MCUs. The MPASM assembler generates relocatable object files for the MPLINK object linker, Intel(R) standard HEX files, MAP files to detail memory usage and symbol reference, absolute LST files that contains source lines and generated machine code and COFF files for debugging. The MPASM assembler features include: * * * * Integration into MPLAB IDE projects User defined macros to streamline assembly code Conditional assembly for multi-purpose source files Directives that allow complete control over the assembly process
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Preliminary
DS41139B-page 81
PIC16C433
11.3 MPLAB C17 and MPLAB C18 C Compilers 11.6 MPLAB ASM30 Assembler, Linker, and Librarian
The MPLAB C17 and MPLAB C18 Code Development Systems are complete ANSI C compilers for Microchip's PIC17CXXX and PIC18CXXX family of microcontrollers. These compilers provide powerful integration capabilities, superior code optimization and ease of use not found with other compilers. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger. MPLAB ASM30 assembler produces relocatable machine code from symbolic assembly language for dsPIC30F devices. MPLAB C30 compiler uses the assembler to produce it's object file. The assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. Notable features of the assembler include: * * * * * * Support for the entire dsPIC30F instruction set Support for fixed-point and floating-point data Command line interface Rich directive set Flexible macro language MPLAB IDE compatibility
11.4
MPLINK Object Linker/ MPLIB Object Librarian
The MPLINK object linker combines relocatable objects created by the MPASM assembler and the MPLAB C17 and MPLAB C18 C compilers. It can link relocatable objects from pre-compiled libraries, using directives from a linker script. The MPLIB object librarian manages the creation and modification of library files of pre-compiled code. When a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. This allows large libraries to be used efficiently in many different applications. The object linker/library features include: * Efficient linking of single libraries instead of many smaller files * Enhanced code maintainability by grouping related modules together * Flexible creation of libraries with easy module listing, replacement, deletion and extraction
11.7
MPLAB SIM Software Simulator
The MPLAB SIM software simulator allows code development in a PC hosted environment by simulating the PICmicro series microcontrollers on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a file, or user defined key press, to any pin. The execution can be performed in Single-Step, Execute Until Break, or Trace mode. The MPLAB SIM simulator fully supports symbolic debugging using the MPLAB C17 and MPLAB C18 C Compilers, as well as the MPASM assembler. The software simulator offers the flexibility to develop and debug code outside of the laboratory environment, making it an excellent, economical software development tool.
11.5
MPLAB C30 C Compiler
11.8
MPLAB SIM30 Software Simulator
The MPLAB C30 C compiler is a full-featured, ANSI compliant, optimizing compiler that translates standard ANSI C programs into dsPIC30F assembly language source. The compiler also supports many commandline options and language extensions to take full advantage of the dsPIC30F device hardware capabilities, and afford fine control of the compiler code generator. MPLAB C30 is distributed with a complete ANSI C standard library. All library functions have been validated and conform to the ANSI C library standard. The library includes functions for string manipulation, dynamic memory allocation, data conversion, timekeeping, and math functions (trigonometric, exponential and hyperbolic). The compiler provides symbolic information for high level source debugging with the MPLAB IDE.
The MPLAB SIM30 software simulator allows code development in a PC hosted environment by simulating the dsPIC30F series microcontrollers on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a file, or user defined key press, to any of the pins. The MPLAB SIM30 simulator fully supports symbolic debugging using the MPLAB C30 C Compiler and MPLAB ASM30 assembler. The simulator runs in either a Command Line mode for automated tasks, or from MPLAB IDE. This high speed simulator is designed to debug, analyze and optimize time intensive DSP routines.
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Preliminary
2002 Microchip Technology Inc.
PIC16C433
11.9 MPLAB ICE 2000 High Performance Universal In-Circuit Emulator 11.11 MPLAB ICD 2 In-Circuit Debugger
Microchip's In-Circuit Debugger, MPLAB ICD 2, is a powerful, low cost, run-time development tool, connecting to the host PC via an RS-232 or high speed USB interface. This tool is based on the FLASH PICmicro MCUs and can be used to develop for these and other PICmicro microcontrollers. The MPLAB ICD 2 utilizes the in-circuit debugging capability built into the FLASH devices. This feature, along with Microchip's In-Circuit Serial ProgrammingTM (ICSPTM) protocol, offers cost effective in-circuit FLASH debugging from the graphical user interface of the MPLAB Integrated Development Environment. This enables a designer to develop and debug source code by setting breakpoints, single-stepping and watching variables, CPU status and peripheral registers. Running at full speed enables testing hardware and applications in real-time. MPLAB ICD 2 also serves as a development programmer for selected PICmicro devices.
The MPLAB ICE 2000 universal in-circuit emulator is intended to provide the product development engineer with a complete microcontroller design tool set for PICmicro microcontrollers. Software control of the MPLAB ICE 2000 in-circuit emulator is advanced by the MPLAB Integrated Development Environment, which allows editing, building, downloading and source debugging from a single environment. The MPLAB ICE 2000 is a full-featured emulator system with enhanced trace, trigger and data monitoring features. Interchangeable processor modules allow the system to be easily reconfigured for emulation of different processors. The universal architecture of the MPLAB ICE in-circuit emulator allows expansion to support new PICmicro microcontrollers. The MPLAB ICE 2000 in-circuit emulator system has been designed as a real-time emulation system with advanced features that are typically found on more expensive development tools. The PC platform and Microsoft(R) Windows 32-bit operating system were chosen to best make these features available in a simple, unified application.
11.12 PRO MATE II Universal Device Programmer
The PRO MATE II is a universal, CE compliant device programmer with programmable voltage verification at VDDMIN and VDDMAX for maximum reliability. It features an LCD display for instructions and error messages and a modular detachable socket assembly to support various package types. In Stand-Alone mode, the PRO MATE II device programmer can read, verify, and program PICmicro devices without a PC connection. It can also set code protection in this mode.
11.10 MPLAB ICE 4000 High Performance Universal In-Circuit Emulator
The MPLAB ICE 4000 universal in-circuit emulator is intended to provide the product development engineer with a complete microcontroller design tool set for highend PICmicro microcontrollers. Software control of the MPLAB ICE in-circuit emulator is provided by the MPLAB Integrated Development Environment, which allows editing, building, downloading and source debugging from a single environment. The MPLAB ICD 4000 is a premium emulator system, providing the features of MPLAB ICE 2000, but with increased emulation memory and high speed performance for dsPIC30F and PIC18XXXX devices. Its advanced emulator features include complex triggering and timing, up to 2 Mb of emulation memory, and the ability to view variables in real-time. The MPLAB ICE 4000 in-circuit emulator system has been designed as a real-time emulation system with advanced features that are typically found on more expensive development tools. The PC platform and Microsoft Windows 32-bit operating system were chosen to best make these features available in a simple, unified application.
11.13 PICSTART Plus Development Programmer
The PICSTART Plus development programmer is an easy-to-use, low cost, prototype programmer. It connects to the PC via a COM (RS-232) port. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. The PICSTART Plus development programmer supports most PICmicro devices up to 40 pins. Larger pin count devices, such as the PIC16C92X and PIC17C76X, may be supported with an adapter socket. The PICSTART Plus development programmer is CE compliant.
2002 Microchip Technology Inc.
Preliminary
DS41139B-page 83
PIC16C433
11.14 PICDEM 1 PICmicro Demonstration Board
The PICDEM 1 demonstration board demonstrates the capabilities of the PIC16C5X (PIC16C54 to PIC16C58A), PIC16C61, PIC16C62X, PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and PIC17C44. All necessary hardware and software is included to run basic demo programs. The sample microcontrollers provided with the PICDEM 1 demonstration board can be programmed with a PRO MATE II device programmer, or a PICSTART Plus development programmer. The PICDEM 1 demonstration board can be connected to the MPLAB ICE in-circuit emulator for testing. A prototype area extends the circuitry for additional application components. Features include an RS-232 interface, a potentiometer for simulated analog input, push button switches and eight LEDs.
11.16 PICDEM 2 Plus Demonstration Board
The PICDEM 2 Plus demonstration board supports many 18-, 28-, and 40-pin microcontrollers, including PIC16F87X and PIC18FXX2 devices. All the necessary hardware and software is included to run the demonstration programs. The sample microcontrollers provided with the PICDEM 2 demonstration board can be programmed with a PRO MATE II device programmer, PICSTART Plus development programmer, or MPLAB ICD 2 with a Universal Programmer Adapter. The MPLAB ICD 2 and MPLAB ICE in-circuit emulators may also be used with the PICDEM 2 demonstration board to test firmware. A prototype area extends the circuitry for additional application components. Some of the features include an RS-232 interface, a 2 x 16 LCD display, a piezo speaker, an on-board temperature sensor, four LEDs, and sample PIC18F452 and PIC16F877 FLASH microcontrollers.
11.15 PICDEM.net Internet/Ethernet Demonstration Board
The PICDEM.net demonstration board is an Internet/ Ethernet demonstration board using the PIC18F452 microcontroller and TCP/IP firmware. The board supports any 40-pin DIP device that conforms to the standard pinout used by the PIC16F877 or PIC18C452. This kit features a user friendly TCP/IP stack, web server with HTML, a 24L256 Serial EEPROM for Xmodem download to web pages into Serial EEPROM, ICSP/MPLAB ICD 2 interface connector, an Ethernet interface, RS-232 interface, and a 16 x 2 LCD display. Also included is the book and CD-ROM "TCP/IP Lean, Web Servers for Embedded Systems," by Jeremy Bentham
11.17 PICDEM 3 PIC16C92X Demonstration Board
The PICDEM 3 demonstration board supports the PIC16C923 and PIC16C924 in the PLCC package. All the necessary hardware and software is included to run the demonstration programs.
11.18 PICDEM 17 Demonstration Board
The PICDEM 17 demonstration board is an evaluation board that demonstrates the capabilities of several Microchip microcontrollers, including PIC17C752, PIC17C756A, PIC17C762 and PIC17C766. A programmed sample is included. The PRO MATE II device programmer, or the PICSTART Plus development programmer, can be used to reprogram the device for user tailored application development. The PICDEM 17 demonstration board supports program download and execution from external on-board FLASH memory. A generous prototype area is available for user hardware expansion.
DS41139B-page 84
Preliminary
2002 Microchip Technology Inc.
PIC16C433
11.19 PICDEM 18R PIC18C601/801 Demonstration Board
The PICDEM 18R demonstration board serves to assist development of the PIC18C601/801 family of Microchip microcontrollers. It provides hardware implementation of both 8-bit Multiplexed/De-multiplexed and 16-bit Memory modes. The board includes 2 Mb external FLASH memory and 128 Kb SRAM memory, as well as serial EEPROM, allowing access to the wide range of memory types supported by the PIC18C601/801.
11.21 PICDEM USB PIC16C7X5 Demonstration Board
The PICDEM USB Demonstration Board shows off the capabilities of the PIC16C745 and PIC16C765 USB microcontrollers. This board provides the basis for future USB products.
11.22 Evaluation and Programming Tools
In addition to the PICDEM series of circuits, Microchip has a line of evaluation kits and demonstration software for these products. * KEELOQ evaluation and programming tools for Microchip's HCS Secure Data Products * CAN developers kit for automotive network applications * Analog design boards and filter design software * PowerSmart battery charging evaluation/ calibration kits * IrDA(R) development kit * microID development and RFLabTM development software * SEEVAL(R) designer kit for memory evaluation and endurance calculations * PICDEM MSC demo boards for Switching mode power supply, high power IR driver, delta sigma ADC, and flow rate sensor Check the Microchip web page and the latest Product Line Card for the complete list of demonstration and evaluation kits.
11.20 PICDEM LIN PIC16C43X Demonstration Board
The powerful LIN hardware and software kit includes a series of boards and three PICmicro microcontrollers. The small footprint PIC16C432 and PIC16C433 are used as slaves in the LIN communication and feature on-board LIN transceivers. A PIC16F874 FLASH microcontroller serves as the master. All three microcontrollers are programmed with firmware to provide LIN bus communication.
2002 Microchip Technology Inc.
Preliminary
DS41139B-page 85
PIC14000
PI18CX01
PIC16C5X
PIC16C6X
PIC16C7X
PIC16C8X
PIC16C43X
PIC16F62X
PIC16C7X5
PIC12FXXX
PIC16C7XX
PIC16F8XX
PIC16C9XX
PIC17C4X
PIC17C7XX
PIC18CXX2
PIC12CXXX
PIC16CXXX
PIC18FXXX dsPIC30F
TABLE 11-1:
Software Tools
Programmers Debugger Emulators
Demo Boards and Eval Kits
DS41139B-page 86 ** * ** **
MPLAB Integrated Development Environment
MPLAB C17 C Compiler
MPLAB C18 C Compiler
PIC16C433
MPASM Assembler/ MPLINK Object Linker
MPLAB C30 C Compiler
MPLAB ASM30 Assembler/Linker/Librarian
MPLAB ICE 2000 In-Circuit Emulator
MPLAB ICE 4000 In-Circuit Emulator
MPLAB ICD 2 In-Circuit Debugger
*
PICSTART Plus Entry Level Development Programmer
DEVELOPMENT TOOLS FROM MICROCHIP
Preliminary

PRO MATE II Universal Device Programmer
PICDEM 1 Demonstration Board
PICDEM.net Demonstration Board
PICDEM 2 Plus Demonstration Board
PICDEM 3 Demonstration Board
PICDEM 14A Demonstration Board
PICDEM 17 Demonstration Board
PICDEM 18R Demonstration Board
PICDEM LIN Demonstration Board
PICDEM USB Demonstration Board
2002 Microchip Technology Inc.
* Contact the Microchip web site at www.microchip.com for information on how to use the MPLAB ICD In-Circuit Debugger (DV164001) with PIC16C62, 63, 64, 65, 72, 73, 74, 76, 77. ** Contact Microchip Technology Inc. for availability date. Development tool is available on select devices.
PIC16C433
12.0 ELECTRICAL SPECIFICATIONS FOR PIC16C433
Absolute Maximum Ratings Ambient Temperature under bias .............................................................................................................. -40 to +125C Storage Temperature ................................................................................................................................ -65 to +150C Voltage on any pin with respect to VSS (except VDD and MCLR) .......................................................-0.6V to VDD +0.6V Voltage on VDD with respect to VSS ................................................................................................................ 0 to +7.0V Voltage on MCLR with respect to VSS* ..............................................................................................................0 to +14V Voltage on LIN and VBAT with respect to VSS .............................................................................................................40V Total power Dissipation .............................................................................................................................................1.0W Maximum Current out of VSS pin ..........................................................................................................................300 mA Maximum Current into VDD pin .............................................................................................................................250 mA Input Clamp Current, IIK (VI <0 or VI> VDD) ...................................................................................................................... 20 mA Output Clamp Current, IOK (VO <0 or VO>VDD)................................................................................................................ 20 mA Maximum Output Current sunk by any I/O pin ........................................................................................................25 mA Maximum Output Current sourced by VDD (sourced by VDD) .................................................................................25 mA Maximum Output Current sourced by any I/O pin (sourced by VDD) ......................................................................25 mA Maximum Current sunk by GPIO (sourced by VDD)..............................................................................................200 mA Maximum Current sourced by GPIO (sourced by VDD) ........................................................................................200 mA Maximum Current sourced by VBAT (sourced by VBAT) ........................................................................................200 mA Maximum Current sunk by LIN (sourced by VBAT)................................................................................................200 mA Maximum Current sunk by BACT...........................................................................................................................1.8 mA * Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latchup. Thus, a series resistor of 50-100 should be used when applying a low level to the MCLR pin, rather than pulling this pin directly to VSS.. NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions, above those indicated in the operation listings of this specification, is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
2002 Microchip Technology Inc.
Preliminary
DS41139B-page 87
PIC16C433
FIGURE 12-1: PIC16C433 VOLTAGE-FREQUENCY GRAPH, -40C TA +125C
6.0 5.5 5.0 VDD (Volts) 4.5 4.0 3.5 3.0 2.5 2.0 0 4 10 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: The maximum rated speed of the part limits the permissible combinations of voltage and frequency. Please reference the Product Identification System, page 123 for the maximum rated speed of the parts. 20 25
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Preliminary
2002 Microchip Technology Inc.
PIC16C433
12.1 DC Characteristics PIC16C433 (Industrial, Extended)
Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C TA +85C for industrial -40C TA +125C for extended Characteristic Supply Voltage Operating Battery Voltage RAM Data Retention Voltage (Note 1) VDD Start Voltage to ensure Power-on Reset VDD Rise Rate to ensure Power-on Reset Supply Current (Note 2) 0.05* -- -- -- D010A D020 D021 D021B D022 IPD Power-down Current (Note 4) -- -- -- -- -- -- -- -- 1.2 1.2 2.2 -- 0.25 2 0.8 3 2.2 2.2 4 3.5 3.5 9 -- 7 14 9 16 5 6 11 Min 4.5 8.0 13.8 1.5* VSS Typ Max 5.5 18 Units V V V V Device in SLEEP mode See Section 9.4 for details Conditions DC Characteristics Parm No. D001 D001A D002 D003 D004 D010 D010C Sym VDD VBAT VDR VPOR SVDD IDD
V/ms See Section 9.4 for details mA mA mA -- A A A A A A A VDD = 4.5V, Industrial, WDT disabled VDD = 4.5V, Extended, WDT disabled VDD = 5.5V, Industrial, WDT disabled VDD = 5.5V, Extended, WDT disabled VDD = 4.5V, Commercial VDD = 4.5V, Industrial VDD = 4.5V, Extended FOSC = 4 MHz, VDD = 4.5V XT and EXTRC mode (Note 3) FOSC = 4 MHz, VDD = 4.5V INTRC mode (Note 5) FOSC = 10 MHz, VDD = 5.5V HS mode
IWDT
Watchdog Timer Current
These parameters are characterized but not tested. Data in Typical ("Typ") column is based on characterization results at 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus loading, oscillator type, bus rate, internal code execution pattern and temperature, also have an impact on the current consumption. a) The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT disabled. b) For standby current measurements, the conditions are the same, except that the device is in SLEEP mode.
*
c)
IDD values include LIN bus transceiver current as defined by D313 in Table 12-1.
3: For EXTRC osc configuration, current through REXT is not included. The current through the resistor can be estimated by the formula: Ir = VDD/2REXT (mA) with REXT in kOhm. 4: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD or VSS. However, The LIN Bus transceiver will still draw current. Please refer to Table 12-1. 5: INTRC calibration value is for 4 MHz nominal at 5V, 25C.
2002 Microchip Technology Inc.
Preliminary
DS41139B-page 89
PIC16C433
12.2 DC Characteristics: PIC16C433 (Industrial, Extended)
Standard Operating Conditions (unless otherwise specified) Operating temperature -40C TA +85C (industrial) -40C TA +125C (extended) Operating voltage VDD range as described in DC spec Section 12.1. Sym Min Typ Max Units Conditions
DC CHARACTERISTICS Param No.
Characteristic
Input Low Voltage I/O ports with TTL buffer with Schmitt Trigger buffer MCLR, GP2/T0CKI/AN2/INT (in EXTRC mode) OSC1 (in EXTRC mode) OSC1 (in XT, HS, and LP) Input High Voltage I/O ports with TTL buffer
VIL VSS VSS VSS VSS VSS VSS VIH 2.0V 0.25VDD + 0.8V 0.8VDD 0.8VDD 0.7VDD 0.9VDD IIL
D030 D031 D032 D033 D033
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
250
0.8V 0.15VDD 0.2VDD 0.2VDD 0.2VDD 0.3VDD
V V V V
For 4.5V VDD 5.5V otherwise
V
(Note 1) (Note 1)
D040 D040A D041 with Schmitt Trigger buffer D042 MCLR, GP2/T0CKI/AN2/INT D042A OSC1 (XT, HS, and LP) D043 OSC1 (in EXTRC mode) Input Leakage Current (Notes 2, 3) D060 I/O ports D061 D061A D062 D063 D070 GP3/MCLR (Note 5) GP3 (Note 6) GP2/T0CKI OSC1 GPIO weak pull-up current (Note 4) MCLR pull-up current Output Low Voltage I/O ports
VDD VDD VDD VDD VDD VDD +1 +30 +5 +5 +5 400 30 0.6 0.6 0.6 0.6
V V V V V V A A A A A A A V V V V
4.5V VDD 5.5V otherwise For entire VDD range (Note 1)
-- -- -- -- --
IPUR
50
--
VOL
-- -- --
-- -- --
-- --
VSS VPIN VDD, pin at hi-impedance VSS VPIN VDD VSS VPIN VDD VSS VPIN VDD VSS VPIN VDD, XT, HS, and LP osc configuration VDD = 5V, VPIN = VSS VDD = 5V, VPIN = VSS IOL = 8.5 mA, VDD = 4.5V, -40C to +85C IOL = 7.0 mA, VDD = 4.5V, -40C to +125C IOL = 1.6 mA, VDD = 4.5V, -40C to +85C IOL = 1.2 mA, VDD = 4.5V, -40C to +125C
D080 D080A D083 D083A D084
OSC2/CLKOUT
-- --
BACT -- -- 1.0 V Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In EXTRC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16C433 be driven with external clock in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as coming out of the pin. 4: Does not include GP3. For GP3 see parameters D061 and D061A. 5: This specification applies to GP3/MCLR configured as external MCLR and GP3/MCLR configured as input with internal pull-up enabled. 6: This spec. applies when GP3/MCLR is configured as an input with pull-up disabled. The leakage current of the MCLR circuit is higher than the standard I/O logic. 7: LIN characterized 4 MHz, 14.44 VBAT, 5.0V VDD. These parameters are characterized but not tested.
DS41139B-page 90
Preliminary
2002 Microchip Technology Inc.
PIC16C433
12.2 DC Characteristics: PIC16C433 (Industrial, Extended) - Continued
Standard Operating Conditions (unless otherwise specified) Operating temperature -40C TA +85C (industrial) -40C TA +125C (extended) Operating voltage VDD range as described in DC spec Section 12.1. Sym
VOH
DC CHARACTERISTICS Param No.
D090 D090A D092 D092A D093 BACT Capacitive Loading Specs on Output Pins OSC2 pin OSC2/CLKOUT
Characteristic
Output High Voltage I/O ports (Note 3)
Min
VDD - 0.7 VDD - 0.7 VDD - 0.7 VDD - 0.7 4.0
Typ -- --
-- -- --
Max -- --
-- -- --
Units
V V V V V
Conditions
IOH = -3.0 mA, VDD = 4.5V, -40C to +85C IOH = -2.5 mA, VDD = 4.5V, -40C to +125C IOH = 1.3 mA, VDD = 4.5V, -40C to +85C IOH = 1.0 mA, VDD = 4.5V, -40C to +125C IOH = 1.8 mA, VDD = 5.0V
D100
COSC2
--
--
15
pF
D100A LIN D100B BACT D101 All I/O pins Note 1: 2: 3: 4: 5: 6: 7:
CLIN CBACT CIO
-- -- --
-- -- --
50 50 50
pF pF pF
In XT and LP modes when external clock is used to drive OSC1 (Note 7, 8)
Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. In EXTRC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16C433 be driven with external clock in RC mode. The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. Negative current is defined as coming out of the pin. Does not include GP3. For GP3 see parameters D061 and D061A. This specification applies to GP3/MCLR configured as external MCLR and GP3/MCLR configured as input with internal pull-up enabled. This specification applies when GP3/MCLR is configured as an input with pull-up disabled. The leakage current of the MCLR circuit is higher than the standard I/O logic. LIN characterized 4 MHz, 14.44 VBAT, 5.0V VDD. These parameters are characterized but not tested.
8: This parameter is characterized, but not tested.
2002 Microchip Technology Inc.
Preliminary
DS41139B-page 91
PIC16C433
TABLE 12-1: LIN TRANSCEIVER OPERATING SPECIFICATIONS
Operating Conditions: VDD range as described in Table 12-1, -40C < TA < +125C. Param No. D313 D314 Characteristics VDD Quiescent Operating Current VBAT Low Power Current Sym IDD_LIN IBAT Min -- Typ -- Max 1 50 Units mA A LIN Bus recessive Comments
TABLE 12-2:
LIN TRANSCEIVER INTERFACE SPECIFICATIONS
Operating Conditions: VDD range as described in Table 12-1, -40C* These parameters are characterized but not tested.
DS41139B-page 92
Preliminary
2002 Microchip Technology Inc.
PIC16C433
12.3 Timing Parameter Symbology
The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 2. TppS T F Frequency Lowercase letters (pp) and their meanings: pp cc CCP1 ck CLKOUT cs CS di SDI do SDO dt Data in io I/O port mc MCLR Uppercase letters and their meanings: S F Fall H High I Invalid (Hi-impedance) L Low
T
Time
osc rd rw sc ss t0 t1 wr
OSC1 RD RD or WR SCK SS T0CKI T1CKI WR
P R V Z
Period Rise Valid Hi-impedance
FIGURE 12-2: LOAD CONDITIONS
Load condition 1 VDD/2 Load condition 2 VBAT
RL
RL
Pin VSS
CL Pin VSS CL 550 pF - 10 nF
RL = 464 CL = 50 pF 15 pF for all pins except OSC2 for OSC2 output
RL Master = 900 minimum 1000 typical 1100 maximum
2002 Microchip Technology Inc.
Preliminary
DS41139B-page 93
PIC16C433
12.4 Timing Diagrams and Specifications FIGURE 12-3: EXTERNAL CLOCK TIMING
Q4 Q1 Q2 Q3 Q4 Q1
OSC1 1 2 CLKOUT 3 3 4 4
TABLE 12-3:
Parameter No.
CLOCK TIMING REQUIREMENTS
Characteristic External CLKIN Frequency (Note 1) Min Typ Max Units Conditions
Sym FOSC
DC -- 4 MHz XT and EXTRC osc mode DC -- 4 MHz HS osc mode DC -- 10 MHz HS osc mode DC -- 200 kHz LP osc mode Oscillator Frequency DC -- 4 MHz EXTRC osc mode (Note 1) .455 -- 4 MHz XT osc mode 4 -- 4 MHz HS osc mode 4 -- 10 MHz HS osc mode 5 -- 200 kHz LP osc mode 1 TOSC External CLKIN Period 250 -- -- ns XT and EXTRC osc mode (Note 1) 250 -- -- ns HS osc mode 100 -- -- ns HS osc mode 5 -- -- s LP osc mode Oscillator Period 250 -- -- ns EXTRC osc mode (Note 1) 250 -- 10,000 ns XT osc mode 250 -- 250 ns HS osc mode 100 -- 250 ns HS osc mode 5 -- -- s LP osc mode 2 TCY Instruction Cycle Time (Note 1) 400 -- DC ns TCY = 4/FOSC 3 TosL, External Clock in (OSC1) High 50 -- -- ns XT oscillator TosH or Low Time 2.5 -- -- s LP oscillator 10 -- -- ns HS oscillator 4 TosR, External Clock in (OSC1) Rise -- -- 25 ns XT oscillator TosF or Fall Time -- -- 50 ns LP oscillator -- -- 15 ns HS oscillator Data in Typ column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at Min. values with an external clock applied to the OSC1/CLKIN pin. When an external clock input is used, the Max. cycle time limit is DC (no clock) for all devices. OSC2 is disconnected (has no loading) for the PIC16C433.
DS41139B-page 94
Preliminary
2002 Microchip Technology Inc.
PIC16C433
TABLE 12-4: CALIBRATED INTERNAL RC FREQUENCIES - PIC16C433
Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C TA +85C (industrial) Operating Voltage VDD range is described in Section 10.1. Characteristic Internal Calibrated RC Frequency Min* 3.65 Typ(1) 4.00 Max* Units 4.28 Conditions
AC Characteristics Parameter No.
Sym
MHz VDD = 5.0V
* These parameters are characterized but not tested. Note 1: Data in the Typical ("Typ") column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
2002 Microchip Technology Inc.
Preliminary
DS41139B-page 95
PIC16C433
FIGURE 12-4: CLKOUT AND I/O TIMING
Q4 OSC1 10 CLKOUT 13 14 I/O Pin (Input) 17 I/O Pin (Output) Old Value 20, 21 Note: Refer to Figure 12-2 for load conditions. 15 New Value 19 18 12 16 11 Q1 Q2 Q3
TABLE 12-5:
Param Sym No. 10* 11* 12* 13* 14* 15* 16* 17* 18* 19* 20* 21* 22* 23* *
CLKOUT AND I/O TIMING REQUIREMENTS
Characteristic Min -- -- -- -- -- TOSC + 200 0 -- 100 0 -- -- TCY TCY Typ 75 75 35 35 -- -- -- 50 -- -- 10 10 -- -- Max 200 200 100 100 0.5TCY + 20 -- -- 150 -- -- 40 40 -- -- Units Conditions ns ns ns ns ns ns ns ns ns ns ns ns ns ns (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) (Note 1)
TosH2ckL OSC1 to CLKOUT TosH2ckH OSC1 to CLKOUT TckR TckF TckL2ioV TckH2ioI TosH2ioV TosH2ioI CLKOUT rise time CLKOUT fall time CLKOUT to Port out valid Port in hold after CLKOUT OSC1 (Q1 cycle) to Port out valid OSC1 (Q2 cycle) to Port input invalid (I/O in hold time)
TioV2ckH Port in valid before CLKOUT
TioV2osH Port input valid to OSC1 (I/O in setup time) TioR TioF Tinp Trbp Port output rise time Port output fall time GP2/INT pin high or low time GP0/GP1/GP3 change INT high or low time
These parameters are characterized but not tested. Data in Typ column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. These parameters are asynchronous events not related to any internal clock edge. Note 1: Measurements are taken in EXTRC and INTRC modes where CLKOUT output is 4 x TOSC.
DS41139B-page 96
Preliminary
2002 Microchip Technology Inc.
PIC16C433
FIGURE 12-5: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, AND POWER-UP TIMER TIMING
VDD MCLR Internal POR 33 PWRT Timeout OSC Timeout Internal Reset 32 30
Watchdog Timer Reset
34 31 34
36
I/O Pins
TABLE 12-6:
Parameter No. 30 31* 32 33* 34 *
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
Sym TmcL Twdt Tost Tpwrt TIOZ Characteristic MCLR Pulse Width (low) Watchdog Timer Timeout Period (No Prescaler) Oscillation Start-up Timer Period Power up Timer Period I/O Hi-impedance from MCLR Low or Watchdog Timer Reset Min 2 7 -- 28 -- Typ -- 18 1024TOSC 72 -- Max -- 33 -- 132 2.1 Units s ms -- ms s Conditions VDD = 5V, -40C to +125C VDD = 5V, -40C to +125C TOSC = OSC1 period VDD = 5V, -40C to +125C
These parameters are characterized but not tested. Data in Typ column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
2002 Microchip Technology Inc.
Preliminary
DS41139B-page 97
PIC16C433
FIGURE 12-6: TIMER0 CLOCK TIMINGS
GP2/T0CKI
40 42
41
TMR0
Note:
Refer to Figure 12-2 for load conditions.
TABLE 12-7:
Param No. 40* 41* 42* Sym Tt0H Tt0L Tt0P
TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Characteristic T0CKI High Pulse Width No Prescaler With Prescaler T0CKI Low Pulse Width T0CKI Period No Prescaler With Prescaler No Prescaler With Prescaler Min 0.5TCY + 20 10 0.5TCY + 20 10 TCY + 40 Greater of: 20 or TCY + 40 N 2TOSC Typ -- -- -- -- -- -- Max -- -- -- -- -- -- Units ns ns ns ns ns ns N = prescale value (2, 4,..., 256) Conditions Must also meet parameter 42 Must also meet parameter 42
48
TCKE2tmr1 Delay from external clock edge to timer increment
--
7TOSC
--
* These parameters are characterized but not tested. Data in Typ column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
DS41139B-page 98
Preliminary
2002 Microchip Technology Inc.
PIC16C433
TABLE 12-8:
VDD (Volts) 4.5
GPIO PULL-UP RESISTOR RANGES
Temperature (C) -40 25 85 125 -40 25 85 125 Min GP0/GP1 38K 42K 42K 50K 15K 18K 19K 22K GP3 42K 48K 49K 55K 17K 20K 22K 24K 346K 414K 457K 504K 292K 341K 371K 407K 63K 63K 63K 63K 20K 23K 25K 28K 417K 532K 532K 593K 360K 437K 448K 500K Typ Max Units
5.5
-40 285K 25 343K 85 368K 125 431K 5.5 -40 247K 25 288K 85 306K 125 351K * These parameters are characterized but not tested.
4.5
2002 Microchip Technology Inc.
Preliminary
DS41139B-page 99
PIC16C433
TABLE 12-9:
Symbol
dV/dt
LIN bus AC CHARACTERISTICS
Parameter Min. Typ. Max. Unit Note
Slope rising and 1 2 3 V/s (Note 1) falling edges Ttrans_pd Propagation delay of 4 s Ttrans_pd = max(Ttrans_pdr or Ttrans_pdf) transmitter Trec_pd Propagation delay of 6 s Trec_pd = max(Trec_pdr or Trec_pdf) receiver Symmetry of receiver Trec_sym -2 2 s Trec_sym = Trec_pdf - Trec_pdr) propagation delay rising edge w.r.t. falling edge Ttrans_sym Symmetry of transmitter -2 2 s Ttrans_sym = Ttrans_pdf - Trans_pdr) propagation delay rising (Note 2) edge w.r.t. falling edge Note 1: Rising edge is system dependent. Value is characterized but not tested. 2: System dependent.
TABLE 12-10: LIN THERMAL CHARACTERISTICS
Symbol recovery shutdown TTHERM Parameter Recovery Temperature Shutdown Temperature Short Circuit Recovery Time Typ. +135 +155 1.5 Max. Unit C C ms Note Information Parameter Information Parameter Information Parameter
DS41139B-page 100
Preliminary
2002 Microchip Technology Inc.
PIC16C433
FIGURE 12-7: TIMING DIAGRAM
TxD (Input of Physical Layer)
t trans_pdf
t trans_pdr
Bus Signal Rec. Threshold Rec. Threshold
t rec_pdf t rec_pdr
RxD (Physical Layer Output)
2002 Microchip Technology Inc.
Preliminary
DS41139B-page 101
PIC16C433
TABLE 12-11: A/D CONVERTER CHARACTERISTICS:
Param No. A01 A02 A03 A04 A05 A06 A10 A20 A25 A30 A40 Sym NR Characteristic Resolution Min -- -- -- -- -- -- -- 2.5V VSS - 0.3 -- -- Typ -- -- -- -- -- -- guaranteed (Note 3) -- -- -- 180 Max 8 bits < 1 < 1 < 1 < 1 < 1 -- VDD + 0.3 VREF + 0.3 10.0 -- Units bit LSb LSb LSb LSb LSb -- V V k A Average current consumption when A/D is on (Note 1) During VAIN acquisition. Based on differential of VHOLD to VAIN to charge CHOLD, see Section 8.1. During A/D Conversion cycle Conditions VREF = VDD = 5.12V, VSS VAIN VREF VREF = VDD = 5.12V, VSS VAIN VREF VREF = VDD = 5.12V, VSS VAIN VREF VREF = VDD = 5.12V, VSS VAIN VREF VREF = VDD = 5.12V, VSS VAIN VREF VREF = VDD = 5.12V, VSS VAIN VREF VSS VAIN VREF
EABS Total absolute error EIL EDL EFS Integral linearity error Differential linearity error Full scale error
EOFF Offset error -- Monotonicity
VREF Reference voltage VAIN ZAIN IAD Analog input voltage Recommended impedance of analog voltage source A/D conversion current (VDD)
A50
IREF
VREF input current (Note 2)
10
--
1000
A
-- *
--
10
A
These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: When A/D is off, it will not consume any current other than minor leakage current. The power-down current spec includes any such leakage from the A/D module. 2: VREF current is from GP1 pin or VDD pin, whichever is selected as reference input. 3: The A/D conversion result never decreases with an increase in the input voltage, and has no missing codes.
DS41139B-page 102
Preliminary
2002 Microchip Technology Inc.
PIC16C433
FIGURE 12-8: A/D CONVERSION TIMING
BSF ADCON0, GO 134 Q4 130 A/D CLK 132 (TOSC/2)(1) 131 1 TCY
A/D DATA
7
6
5
4
3
2
1
0
ADRES
OLD_DATA
NEW_DATA
ADIF GO SAMPLING STOPPED DONE
SAMPLE Note 1:
If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed.
TABLE 12-12: A/D CONVERSION REQUIREMENTS
Param No. 130 Sym TAD Characteristic A/D clock period Min 1.6 2.0 3.0 131 132 TCNV Conversion time (not including S/H time) (Note 1) 11 (Note 2) 5* Typ -- 4.0 6.0 -- 20 -- Max -- 6.0 9.0 11 -- -- Units s s s Tad s s The minimum time is the amplifier setting time. This may be used if the new input voltage has not changed by more than 1 LSb (i.e., 20.0 mV @ 5.12V) from the last sampled voltage (as stated on CHOLD). If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. Conditions TOSC based, VREF 2.5V A/D RC mode A/D RC mode
TACQ Acquisition time
134
TGO
Q4 to A/D clock start
--
TOSC/2
--
--
135 *
TSWC Switching from convert sample time
1.5
--
--
Tad
These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. This specification ensured by design. Note 1: ADRES register may be read on the following TCY cycle. 2: See Section 8.1 for minimum conditions.
2002 Microchip Technology Inc.
Preliminary
DS41139B-page 103
PIC16C433
NOTES:
DS41139B-page 104
Preliminary
2002 Microchip Technology Inc.
PIC16C433
13.0 DC AND AC CHARACTERISTICS FIGURE 13-2: CALIBRATED INTERNAL RC FREQUENCY RANGE VS. TEMPERATURE (VDD = 2.5V) (INTERNAL RC IS CALIBRATED TO 25C, 5.0V)
4.50 4.40 4.30 4.20
The graphs and tables provided in this section are for design guidance and are not tested. In some graphs or tables, the data presented are outside specified operating range (i.e., outside specified VDD range). This is for information only and devices will operate properly only within the specified range. The data presented in this section is a statistical summary of data collected on units from different lots over a period of time. "Typical" represents the mean of the distribution while "max" or "min" represents (mean + 3) and (mean - 3) respectively, where is standard deviation.
Max.
Frequency (MHz)
FIGURE 13-1: CALIBRATED INTERNAL RC FREQUENCY RANGE VS. TEMPERATURE (VDD = 5.0V) (INTERNAL RC IS CALIBRATED TO 25C, 5.0V)
4.50 4.40 4.30 4.20
4.10 4.00 3.90 3.80 3.70 3.60 3.50
Max.
Frequency (MHz)
4.10 4.00 3.90 3.80 3.70 3.60 3.50
Min.
-40 0 25 85 125
Temperature (Degree C)
Min.
-40
0
25
85
125
Temperature (Degree C)
2002 Microchip Technology Inc.
Preliminary
DS41139B-page 105
PIC16C433
TABLE 13-1: DYNAMIC IDD (TYPICAL) - WDT ENABLED, 25C
Frequency VDD = 2.5V 400 A* 400 A 400 A 15 A VDD = 5.5V 900 A* 900 A 900 A 60 A Oscillator
External RC 4 MHz Internal RC 4 MHz XT 4 MHz LP 32 kHz *Does not include current through external R&C.
FIGURE 13-3: WDT TIMER TIMEOUT PERIOD vs. VDD
55 50 45
FIGURE 13-4: IOH vs. VOH, VDD = 2.5V
-0 -1 -2 -3
40 WDT Period (mS) IOH (mA) 35
Max +125C
-4
Min +125C
-5 -6
Typ +25C
Min +85C
30
Max +85C
-7 -8
25 20
Typ +25C
-9 -10 .5
Max -40C
15
MIn -40C
.75 1.0 1.25 1.5 1.75 2.0 2.25 2.5
10 0 2.5 3.5 4.5 5.5 6.5 VDD (Volts)
VOH (Volts)
DS41139B-page 106
Preliminary
2002 Microchip Technology Inc.
PIC16C433
FIGURE 13-5: IOH vs. VOH, VDD = 3.5V
0
FIGURE 13-7: IOL vs. VOL, VDD = 2.5V
35
-5
Min +125C
30
Max -40C
IOH (mA)
25
-10
IOL (mA)
Min +85C
20
Typ +25C
-15
Typ +25C
15 -20
Max -40C Min +85C
10
Min +125C
-25 1.5 2.0 2.5 3.0 3.5 5
VOH (Volts)
0 0 0.25 0.5 0.75 1.0
FIGURE 13-6: IOH vs. VOH, VDD = 5.5V
0 -5
VOL (Volts)
-10
C 5 12 n+ Mi C 5 +8 in M
p Ty C 5 +2
-15
IOH (mA)
-20
-25
ax -4 0 C
-30
-35
-40 3.5 4.0 4.5 5.0 5.5
M
VOH (Volts)
2002 Microchip Technology Inc.
Preliminary
DS41139B-page 107
PIC16C433
FIGURE 13-8: IOL vs. VOL, VDD = 3.5V
45 55
Max -40C Max -40C
FIGURE 13-9: IOL vs. VOL, VDD = 5.5V
40 50 35
45
40 30
Typ +25C
35
Typ +25C
IOL (mA)
25
IOL (mA)
30
20
25
Min +85C
15
Min +85C Min +125C
20
15
Min +125C
10 10 0 0 0.25 0.5 0.75 1.0 0 0 0.25 0.5
VOL (Volts)
0.75
1.0
VOL (Volts)
DS41139B-page 108
Preliminary
2002 Microchip Technology Inc.
PIC16C433
FIGURE 13-10: VTH (INPUT THRESHOLD VOLTAGE) OF GPIO PINS vs. VDD
1.8
1.6 1.4
Max -40 to +125
Typ +25
VTH (Volts)
1.2 1.0
Min -40 to +125
0.8 0.6 0 2.5
3.5
4.5
5.5
VDD (Volts)
FIGURE 13-11: VIL, VIH OF NMCLR AND T0CKI vs. VDD
3.5 3.0 VIL, VIH (Volts)
VIH Max (-40 to +125) VIH Typ (+25) VIH Min (-40 to +125)
2.5 2.0
VIH Max (-40 to +125)
1.5 1.0 0.5 2.5
VIH Typ (+25) VIH Min (-40 to +125)
3.5
4.5
5.5
VDD (Volts)
2002 Microchip Technology Inc.
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DS41139B-page 109
PIC16C433
FIGURE 13-12:
20 18 16 14 VLIN (V) 12 10 8 6 4 2 120 0 115 120 125 130 135 Temperature (C) 140 135.2 143.1 145 150 155 Temp (Shutdown) Temp (Recover) 135.2 143.1 150.0
LIN TRANSCEIVER SHUTDOWN HYSTERESIS (V) VS. TEMPERATURE (C)
VBAT = 18.0V VDD = 5.0V TXD = 0V
DS41139B-page 110
Preliminary
2002 Microchip Technology Inc.
PIC16C433
14.0
14.1
PACKAGING INFORMATION
Package Marking Information
18-Lead PDIP
XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN
Example
-I/P423 0007CDK
18-Lead SOIC (.300")
XXXXXXXXXXXX XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN
Example
-I/SO218 0007CDK
18-Lead CERDIP Windowed
XXXXXXXX XXXXXXXX YYWWNNN
Example
16C433 /JW 0007CBA
Legend:
XX...X Y YY WW NNN
Customer specific information* Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code
Note:
In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information.
*
Standard PICmicro device marking consists of Microchip part number, year code, week code, and traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price.
2002 Microchip Technology Inc.
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PIC16C433
18-Lead Plastic Dual In-line (P) - 300 mil (PDIP)
E1
D
2 n 1
E
A2 A L A1 B1
c
eB Units Dimension Limits n p
B
p
MIN
Number of Pins Pitch Top to Seating Plane A .140 .170 Molded Package Thickness .115 .145 A2 Base to Seating Plane A1 .015 Shoulder to Shoulder Width E .300 .313 .325 Molded Package Width .240 .250 .260 E1 Overall Length D .890 .898 .905 Tip to Seating Plane L .125 .130 .135 c Lead Thickness .008 .012 .015 Upper Lead Width .045 .058 .070 B1 Lower Lead Width B .014 .018 .022 eB Overall Row Spacing .310 .370 .430 Mold Draft Angle Top 5 10 15 Mold Draft Angle Bottom 5 10 15 * Controlling Parameter Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-007
INCHES* NOM 18 .100 .155 .130
MAX
MIN
MILLIMETERS NOM 18 2.54 3.56 3.94 2.92 3.30 0.38 7.62 7.94 6.10 6.35 22.61 22.80 3.18 3.30 0.20 0.29 1.14 1.46 0.36 0.46 7.87 9.40 5 10 5 10
MAX
4.32 3.68 8.26 6.60 22.99 3.43 0.38 1.78 0.56 10.92 15 15
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Preliminary
2002 Microchip Technology Inc.
PIC16C433
18-Lead Plastic Small Outline (SO) - Wide, 300 mil (SOIC)
E p E1
D
2 B n 1
h
45
c A A2
L A1
Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Chamfer Distance Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic
Units Dimension Limits n p A A2 A1 E E1 D h L f c B
MIN
.093 .088 .004 .394 .291 .446 .010 .016 0 .009 .014 0 0
INCHES* NOM 18 .050 .099 .091 .008 .407 .295 .454 .020 .033 4 .011 .017 12 12
MAX
MIN
.104 .094 .012 .420 .299 .462 .029 .050 8 .012 .020 15 15
MILLIMETERS NOM 18 1.27 2.36 2.50 2.24 2.31 0.10 0.20 10.01 10.34 7.39 7.49 11.33 11.53 0.25 0.50 0.41 0.84 0 4 0.23 0.27 0.36 0.42 0 12 0 12
MAX
2.64 2.39 0.30 10.67 7.59 11.73 0.74 1.27 8 0.30 0.51 15 15
Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-013 Drawing No. C04-051
2002 Microchip Technology Inc.
Preliminary
DS41139B-page 113
PIC16C433
18-Lead Ceramic Dual In-line with Window (JW) - 300 mil (CERDIP)
E1
W2
D
2 n W1 E 1
A c eB A1 B1 B Units Dimension Limits n p A A2 A1 E E1 D L c B1 B eB W1 W2 INCHES* NOM 18 .100 .183 .160 .023 .313 .290 .900 .138 .010 .055 .019 .385 .140 .200 p
A2
L
MIN
MAX
MIN
Number of Pins Pitch Top to Seating Plane Ceramic Package Height Standoff Shoulder to Shoulder Width Ceramic Pkg. Width Overall Length Tip to Seating Plane Lead Thickness Upper Lead Width Lower Lead Width Overall Row Spacing Window Width Window Length * Controlling Parameter Significant Characteristic JEDEC Equivalent: MO-036 Drawing No. C04-010
.170 .155 .015 .300 .285 .880 .125 .008 .050 .016 .345 .130 .190
.195 .165 .030 .325 .295 .920 .150 .012 .060 .021 .425 .150 .210
MILLIMETERS NOM 18 2.54 4.32 4.64 3.94 4.06 0.38 0.57 7.62 7.94 7.24 7.37 22.35 22.86 3.18 3.49 0.20 0.25 1.27 1.40 0.41 0.47 8.76 9.78 3.30 3.56 4.83 5.08
MAX
4.95 4.19 0.76 8.26 7.49 23.37 3.81 0.30 1.52 0.53 10.80 3.81 5.33
DS41139B-page 114
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2002 Microchip Technology Inc.
PIC16C433
APPENDIX A: COMPATIBILITY
To convert code written for PIC16C5X to PIC16C433, the user should take the following steps: 1. 2. Remove any program memory page select operations (PA2, PA1, PA0 bits) for CALL, GOTO. Revisit any computed jump operations (write to PC or add to PC, etc.) to make sure page bits are set properly under the new scheme. Eliminate any data memory page switching. Redefine data variables to reallocate them. Verify all writes to STATUS, OPTION, and FSR registers since these have changed. Change RESET Vector to 0000h.
3. 4. 5.
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DS41139B-page 115
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NOTES:
DS41139B-page 116
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2002 Microchip Technology Inc.
PIC16C433
INDEX
A
A/D Accuracy/Error ........................................................... 49 ADCON0 Register ..................................................... 43 ADIF bit ...................................................................... 45 Analog Input Model Block Diagram ........................... 46 Analog-to-Digital Converter ....................................... 43 Configuring Analog Port Pins .................................... 47 Configuring the Interrupt ............................................ 45 Configuring the Module ............................................. 45 Connection Considerations ....................................... 49 Conversion Clock ...................................................... 47 Conversions ............................................................... 48 Converter Characteristics ........................................ 102 Delays ........................................................................ 46 Effects of a RESET .................................................... 49 Equations ................................................................... 46 Flowchart of A/D Operation ....................................... 50 GO/DONE bit ............................................................. 45 Internal Sampling Switch (Rss) Impedance ............... 46 Operation During SLEEP ........................................... 49 Sampling Requirements ............................................ 46 Sampling Time ........................................................... 46 Source Impedance .................................................... 46 Time Delays ............................................................... 46 Transfer Function ...................................................... 49 ADDLW Instruction ............................................................ 70 ADDWF Instruction ............................................................ 70 ADIE bit .............................................................................. 18 ADIF bit .............................................................................. 19 ADRES Register ...................................................13, 43, 45 ALU ...................................................................................... 7 ANDLW Instruction ............................................................ 70 ANDWF Instruction ............................................................ 70 Application Notes AN546 ........................................................................ 43 AN556 ........................................................................ 22 Architecture Harvard ........................................................................ 7 Overview ...................................................................... 7 von Neumann .............................................................. 7 Assembler MPASM Assembler ................................................... 81 CALFST bit ........................................................................ 21 CALL Instruction ................................................................ 72 CALSLW bit ....................................................................... 21 Carry bit ............................................................................... 7 Clocking Scheme .............................................................. 10 CLRF Instruction ............................................................... 72 CLRW Instruction .............................................................. 72 CLRWDT Instruction ......................................................... 73 Code Examples Changing Prescaler (Timer0 to WDT) ....................... 41 Changing Prescaler (WDT to Timer0) ....................... 41 Indirect Addressing ................................................... 23 Code Protection ...........................................................51, 66 COMF Instruction .............................................................. 73 Computed GOTO .............................................................. 22 Configuration Bits .............................................................. 51
D
DC and AC Characteristics ............................................. 105 DC bit ................................................................................ 15 DC Characteristics PIC16C433 ................................................................ 89 DECF Instruction ............................................................... 73 DECFSZ Instruction .......................................................... 73 Development Support ....................................................3, 81 Diagrams - See Block Diagrams Digit Carry bit ....................................................................... 7 Direct Addressing .............................................................. 23
E
EEPROM Peripheral Operation ......................................... 33 Electrical Characteristics PIC16C433 ................................................................ 87 Errata ................................................................................... 2 External Brown-out Protection Circuit ............................... 59 External Power-on Reset Circuit ....................................... 59
F
Features .............................................................................. 1 FSR Register ........................................................ 13, 14, 23
G
General Description ............................................................. 3 GIE bit ............................................................................... 60 GOTO Instruction .............................................................. 74 GPIF bit ............................................................................. 62 GPIO ...........................................................................25, 57 GPIO Register ................................................................... 13 GPPU bit ........................................................................... 16
B
BCF Instruction .................................................................. 71 Bit Manipulation ................................................................. 68 Block Diagrams Analog Input Model .................................................... 46 On-Chip Reset Circuit ................................................ 55 Timer0 ....................................................................... 37 Timer0/WDT Prescaler .............................................. 40 Watchdog Timer ........................................................ 64 BSF Instruction .................................................................. 71 BTFSC Instruction ............................................................. 71 BTFSS Instruction .............................................................. 72
I
I/O Interfacing .................................................................... 25 I/O Ports ............................................................................ 25 I/O Programming Considerations ...................................... 31 ID Locations ...................................................................... 51 INCF Instruction ................................................................ 74 INCFSZ Instruction ............................................................ 75 In-Circuit Serial Programming .....................................51, 66 INDF Register ..............................................................14, 23 Indirect Addressing ............................................................ 23 Initialization Conditions for All Registers ........................... 57 Instruction Cycle ................................................................ 10 Instruction Flow/Pipelining ................................................. 10 Instruction Format ............................................................. 67
C
C bit ................................................................................... 15 CAL0 bit ............................................................................. 21 CAL1 bit ............................................................................. 21 CAL2 bit ............................................................................. 21 CAL3 bit ............................................................................. 21
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DS41139B-page 117
PIC16C433
Instruction Set ADDLW ...................................................................... 70 ADDWF ...................................................................... 70 ANDLW ...................................................................... 70 ANDWF ...................................................................... 70 BCF ............................................................................ 71 BSF ............................................................................ 71 BTFSC ....................................................................... 71 BTFSS ....................................................................... 72 CALL .......................................................................... 72 CLRF ......................................................................... 72 CLRW ........................................................................ 72 CLRWDT ................................................................... 73 COMF ........................................................................ 73 DECF ......................................................................... 73 DECFSZ .................................................................... 73 GOTO ........................................................................ 74 INCF .......................................................................... 74 INCFSZ ...................................................................... 75 IORLW ....................................................................... 75 IORWF ....................................................................... 75 MOVF ........................................................................ 76 MOVLW ..................................................................... 75 MOVWF ..................................................................... 76 NOP ........................................................................... 76 OPTION ..................................................................... 76 RETFIE ...................................................................... 77 RETLW ...................................................................... 77 RETURN .................................................................... 77 RLF ............................................................................ 78 RRF ........................................................................... 78 SLEEP ....................................................................... 78 SUBLW ...................................................................... 79 SUBWF ...................................................................... 79 SWAPF ...................................................................... 80 TRIS ........................................................................... 80 XORLW ...................................................................... 80 XORWF ..................................................................... 80 Section ....................................................................... 67 INTCON Register ............................................................... 17 INTEDG bit ........................................................................ 16 Internal Sampling Switch (Rss) Impedance ....................... 46 Interrupts ............................................................................ 51 A/D ............................................................................. 60 GP2/INT ..................................................................... 60 GPIO Port .................................................................. 60 Section ....................................................................... 60 TMR0 ......................................................................... 62 TMR0 Overflow .......................................................... 60 IORLW Instruction ............................................................. 75 IORWF Instruction ............................................................. 75 IRP bit ................................................................................ 15 MOVF Instruction .............................................................. 76 MOVLW Instruction ........................................................... 75 MOVWF Instruction ........................................................... 76 MPLAB C17 and MPLAB C18 C Compilers ...................... 82 MPLAB ICD In-Circuit Debugger ....................................... 83 MPLAB ICE High Performance Universal In-Circuit Emulator with MPLAB IDE ................................................................ 83 MPLAB Integrated Development Environment Software .. 81 MPLINK Object Linker/MPLIB Object Librarian ................. 82
N
NOP Instruction ................................................................. 76
O
Opcode .............................................................................. 67 OPTION Instruction ........................................................... 76 OPTION Register .............................................................. 16 Orthogonal ........................................................................... 7 OSC selection ................................................................... 51 OSCCAL Register ............................................................. 21 Oscillator EXTRC ...................................................................... 56 HS ............................................................................. 56 INTRC ....................................................................... 56 LP .............................................................................. 56 XT .............................................................................. 56 Oscillator Configurations ................................................... 52 Oscillator Types EXTRC ...................................................................... 52 HS ............................................................................. 52 INTRC ....................................................................... 52 LP .............................................................................. 52 XT .............................................................................. 52
P
Packaging Information ..................................................... 111 Paging, Program Memory ................................................. 22 PCL ................................................................................... 68 PCL Register ........................................................ 13, 14, 22 PCLATH ............................................................................ 57 PCLATH Register ................................................. 13, 14, 22 PCON Register ............................................................20, 56 PD bit ...........................................................................15, 54 PICDEM 1 Low Cost PICmicro Demonstration Board ....... 84 PICDEM 17 Demonstration Board .................................... 84 PICDEM 2 Low Cost PIC16CXX Demonstration Board .... 84 PICSTART Plus Entry Level Development Programmer .. 83 PIE1 Register .................................................................... 18 Pinout Description PIC16C433 .................................................................. 9 PIR1 Register .................................................................... 19 POP ................................................................................... 22 POR ................................................................................... 56 Oscillator Start-up Timer (OST) ...........................51, 56 Power Control Register (PCON) ............................... 56 Power-on Reset (POR) ................................ 51, 56, 57 Power-up Timer (PWRT) .....................................51, 56 Power-up-Timer (PWRT) ........................................... 56 Time-out Sequence ................................................... 56 Time-out Sequence on Power-up .............................. 58 TO ............................................................................. 54 Power ................................................................................ 54 Power-down Mode (SLEEP) ............................................. 64 Power-on Reset (POR) Time-out (TO Bit) ....................................................... 15 Prescaler, Switching Between Timer0 and WDT .............. 41
L
LIN Hardware Interface ...................................................... 33 LIN Interfacing ................................................................... 33 LIN Protocol ....................................................................... 33 Loading of PC .................................................................... 22
M
MCLR .......................................................................... 54, 57 Memory Data Memory ............................................................. 11 Program Memory ....................................................... 11 Register File Map PIC16C433 ........................................................ 12
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2002 Microchip Technology Inc.
PIC16C433
PRO MATE II Universal Device Programmer .................... 83 Program Branches ............................................................... 7 Program Memory Paging ....................................................................... 22 Program Verification .......................................................... 66 PS0 bit ............................................................................... 16 PS1 bit ............................................................................... 16 PS2 bit ............................................................................... 16 PSA bit ............................................................................... 16 PUSH ................................................................................. 22 External Clock ................................................... 39 External Clock Timing ....................................... 39 Increment Delay ................................................ 39 Interrupt ............................................................. 37 Interrupt Timing ................................................. 38 Prescaler ........................................................... 40 Prescaler Block Diagram ................................... 40 Section .............................................................. 37 Switching Prescaler Assignment ....................... 41 Synchronization ................................................. 39 T0CKI ................................................................ 39 T0IF ................................................................... 62 Timing ............................................................... 37 TMR0 Interrupt .................................................. 62 Timing Diagrams A/D Conversion ....................................................... 103 CLKOUT and I/O ....................................................... 96 External Clock Timing ............................................... 94 Time-out Sequence ................................................... 58 Timer0 ....................................................................... 37 Timer0 Interrupt Timing ............................................. 38 Timer0 with External Clock ....................................... 39 Wake-up from SLEEP via Interrupt ........................... 65 TO bit ................................................................................. 15 TOSE bit ............................................................................ 16 TRIS Instruction ................................................................. 80 TRIS Register ....................................................... 14, 25, 30 Two's Complement .............................................................. 7
R
RC Oscillator ...................................................................... 53 Read Modify Write ............................................................. 31 Read-Modify-Write ............................................................. 31 Register File ....................................................................... 11 Registers Map PIC16C433 ........................................................ 12 RESET Conditions ..................................................... 57 RESET ........................................................................ 51, 54 RESET Conditions for Special Registers ........................... 57 RETFIE Instruction ............................................................ 77 RETLW Instruction ............................................................. 77 RETURN Instruction .......................................................... 77 RLF Instruction .................................................................. 78 RP0 bit ........................................................................ 11, 15 RP1 bit ............................................................................... 15 RRF Instruction .................................................................. 78
S
Services One-Time-Programmable (OTP) ................................. 5 Quick-Turnaround-Production (QTP) .......................... 5 Serialized Quick-Turnaround Production (SQTP) ....... 5 SFR .................................................................................... 68 SFR As Source/Destination ............................................... 68 SLEEP ........................................................................ 51, 54 SLEEP Instruction .............................................................. 78 Software Simulator (MPLAB SIM) ..................................... 82 Special Features of the CPU ............................................. 51 Special Function Register PIC16C433 ................................................................ 13 Special Function Registers ................................................ 68 Special Function Registers, Section .................................. 12 Stack .................................................................................. 22 Overflows ................................................................... 22 Underflow .................................................................. 22 STATUS Register .............................................................. 15 DC Bit ................................................................. 15, 43 IRP Bit ..........................................................15, 43, 44 TO Bit ........................................................................ 15 Z Bit .................................................................... 15, 43 SUBLW Instruction ............................................................ 79 SUBWF Instruction ............................................................ 79 SWAPF Instruction ............................................................ 80
U
UV Erasable Devices .......................................................... 5
W
W Register ALU ............................................................................. 7 Wake-up from SLEEP ....................................................... 64 Watchdog Timer (WDT) ................................ 51, 54, 57, 63 WDT .................................................................................. 57 Block Diagram ........................................................... 64 Period ........................................................................ 63 Programming Considerations .................................... 63 Timeout ..................................................................... 57 WWW, On-Line Support ...................................................... 2
X
XORLW Instruction ............................................................ 80 XORWF Instruction ........................................................... 80
Z
Z bit ................................................................................... 15 Zero bit ................................................................................ 7
T
T0CS bit ............................................................................. 16 TAD ..................................................................................... 47 Thermal Shut-down ........................................................... 34 Timer0 RTCC ......................................................................... 57 Timers Timer0 Block Diagram ................................................... 37
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NOTES:
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Preliminary
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PIC16C433
ON-LINE SUPPORT
Microchip provides on-line support on the Microchip World Wide Web site. The web site is used by Microchip as a means to make files and information easily available to customers. To view the site, the user must have access to the Internet and a web browser, such as Netscape(R) or Microsoft(R) Internet Explorer. Files are also available for FTP download from our FTP site.
SYSTEMS INFORMATION AND UPGRADE HOT LINE
The Systems Information and Upgrade Line provides system users a listing of the latest versions of all of Microchip's development systems software products. Plus, this line provides information on how customers can receive the most current upgrade kits.The Hot Line Numbers are: 1-800-755-2345 for U.S. and most of Canada, and 1-480-792-7302 for the rest of the world.
Connecting to the Microchip Internet Web Site
The Microchip web site is available at the following URL: www.microchip.com The file transfer site is available by using an FTP service to connect to: ftp://ftp.microchip.com The web site and file transfer site provide a variety of services. Users may download files for the latest Development Tools, Data Sheets, Application Notes, User's Guides, Articles and Sample Programs. A variety of Microchip specific business information is also available, including listings of Microchip sales offices, distributors and factory representatives. Other data available for consideration is: * Latest Microchip Press Releases * Technical Support Section with Frequently Asked Questions * Design Tips * Device Errata * Job Postings * Microchip Consultant Program Member Listing * Links to other useful web sites related to Microchip Products * Conferences for products, Development Systems, technical information and more * Listing of seminars and events
092002
2002 Microchip Technology Inc.
Preliminary
DS41139B-page121
PIC16C433
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. To: RE: Technical Publications Manager Reader Response Total Pages Sent ________
From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ Application (optional): Would you like a reply? Device: PIC16C433 Questions: 1. What are the best features of this document? Y N Literature Number: DS41139B FAX: (______) _________ - _________
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
DS41139B-page122
Preliminary
2002 Microchip Technology Inc.
PIC16C433
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device X Temperature Range /XX Package XXX Pattern Examples:
a) b) Device PIC16C433 PIC16C433 (Tape & reel for SOIC only) PIC16C433-I/P = Industrial temp., PDIP, 4 MHz - 10 MHz, normal VDD limits PIC16C433-E/P = Extended temp., PDIP, 4 MHz - 10 MHz, normal VDD limits
Temperature Range
I E
= -40C to +85C = -40C to +125C
Package
P JW* SM
= = =
PDIP Windowed CERDIP SOIC
Pattern
Special Requirements
* JW Devices are UV erasable and can be programmed to any device configuration. JW Devices meet the electrical requirement of each oscillator type.
Sales and Support
Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. 2. 3. Your local Microchip sales office The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277 The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. New Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
2002 Microchip Technology Inc.
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WORLDWIDE SALES AND SERVICE
AMERICAS
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India
Microchip Technology Inc. India Liaison Office Divyasree Chambers 1 Floor, Wing A (A3/A4) No. 11, O'Shaugnessey Road Bangalore, 560 025, India Tel: 91-80-2290061 Fax: 91-80-2290062
United Kingdom
Microchip Ltd. 505 Eskdale Road Winnersh Triangle Wokingham Berkshire, England RG41 5TU Tel: 44 118 921 5869 Fax: 44-118 921-5820
12/05/02
DS41139B-page 124
Preliminary
2002 Microchip Technology Inc.

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